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1. 发明申请

US20220391110A1 ADAPTIVE COMPRESSION FOR ACCELERATOR DEVICES 有权
公开(公告)号：US20220391110A1
公开(公告)日：2022-12-08
申请号：US17865594
申请日：2022-07-15
申请人： Intel Corporation
发明人： Fei Wang , John Browne , Laurent Coquerel
IPC分类号： G06F3/06
摘要： An accelerator device may access an input data chunk to be compressed by the accelerator device. The accelerator device may access an entropy value for the input data chunk. The accelerator device may compress the input data chunk or return an indication that the input data chunk will not be compressed based on the entropy value and an entropy threshold.

2. 发明授权

US11388074B2 Technologies for performance monitoring and management with empty polling 有权
公开(公告)号：US11388074B2
公开(公告)日：2022-07-12
申请号：US16381237
申请日：2019-04-11
申请人： Intel Corporation
发明人： Peter McCarthy , Chris MacNamara , John Browne , Liang J. Ma , Liam Day
IPC分类号： G06F1/32 , H04L43/00 , H04L43/10 , H04L41/0833 , H04L43/022 , H04L43/16 , G06F1/3209
摘要： Technologies for performance monitoring include a computing device having multiple processor cores. The computing device performs a training workload with a processor core by continuously polling an empty input queue. The computing device determines empty polling thresholds based on the empty polling workload. The computing device performs a packet processing workload with one or more processor cores by continuously polling input queues associated with network traffic. The computing device compares a measured number of empty polls performed by the packet processing workload against the empty polling thresholds. The computing device configures power management of one or more processor cores in response to the comparison. The computing device may determine empty polling trends and compare the measured number of empty polls and the empty polling trends to the empty polling thresholds. Other embodiments are described and claimed.

3. 发明申请

US20210117191A1 METHODS AND APPARATUS TO CONTROL EXECUTION OF TASKS IN A COMPUTING SYSTEM 有权
公开(公告)号：US20210117191A1
公开(公告)日：2021-04-22
申请号：US17133305
申请日：2020-12-23
申请人： Intel Corporation
发明人： Andrew Cunningham , Patrick Fleming , Naveen Lakkakula , Richard Guerin , Charitra Sankar , Stephen Doyle , Ralph Castro , John Browne
IPC分类号： G06F9/30 , G06F9/448 , G06F9/48 , G06F11/10
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to control execution of tasks in a computing system. The methods, apparatus, systems and articles of manufacture include at least one storage device and at least one processor to, execute instructions to at least obtain a request to perform an inverse operation on a data flow, the data flow previously transformed during a forward operation, determine a first processor core that executed the forward operation, the data flow including an identifier of the first processor core, and transmit the data flow to a second processor core to perform the inverse operation.

4. 发明申请

US20190044860A1 TECHNOLOGIES FOR PROVIDING ADAPTIVE POLLING OF PACKET QUEUES 审中-公开
公开(公告)号：US20190044860A1
公开(公告)日：2019-02-07
申请号：US16011103
申请日：2018-06-18
申请人： Intel Corporation
发明人： Chris MacNamara , John Browne , Tomasz Kantecki , Ciara Loftus , John Barry , Patrick Connor , Patrick Fleming
IPC分类号： H04L12/801 , H04L12/861 , H04L12/841
摘要： Technologies for providing adaptive polling of packet queues include a compute device. The compute device includes a network interface controller and a compute engine that includes a set of cores and a memory that includes a queue to store packets received by the network interface controller. The compute engine is configured to determine a predicted time period for the queue to receive packets without overflowing, execute, during the time period and with a core that is assigned to periodically poll the queue for packets, a workload, and poll, with the assigned core, the queue to remove the packets from the queue. Other embodiments are also described and claimed.

5. 发明申请

US20190042310A1 TECHNOLOGIES FOR POWER-AWARE SCHEDULING FOR NETWORK PACKET PROCESSING 审中-公开
公开(公告)号：US20190042310A1
公开(公告)日：2019-02-07
申请号：US15951650
申请日：2018-04-12
申请人： Intel Corporation
发明人： John Browne , Chris MacNamara , Tomasz Kantecki , Peter McCarthy , Ma Liang , Mairtin O'Loingsigh , Rory Sexton , John Griffin , Nemanja Marjanovic , David Hunt
IPC分类号： G06F9/48 , G06F1/32 , H04L12/851
摘要： Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.

6. 发明申请

US20220393960A1 TECHNOLOGIES FOR PERFORMANCE MONITORING AND MANAGEMENT WITH EMPTY POLLING 有权
公开(公告)号：US20220393960A1
公开(公告)日：2022-12-08
申请号：US17846947
申请日：2022-06-22
申请人： Intel Corporation
发明人： Peter McCarthy , Chris MacNamara , John Browne , Liang J. Ma , Liam Day
IPC分类号： H04L43/10 , H04L41/0833 , H04L43/022 , H04L43/16 , G06F1/3209
摘要： Technologies for performance monitoring include a computing device having multiple processor cores. The computing device performs a training workload with a processor core by continuously polling an empty input queue. The computing device determines empty polling thresholds based on the empty polling workload. The computing device performs a packet processing workload with one or more processor cores by continuously polling input queues associated with network traffic. The computing device compares a measured number of empty polls performed by the packet processing workload against the empty polling thresholds. The computing device configures power management of one or more processor cores in response to the comparison. The computing device may determine empty polling trends and compare the measured number of empty polls and the empty polling trends to the empty polling thresholds. Other embodiments are described and claimed.

7. 发明申请

US20220368348A1 UNIVERSAL DECOMPRESSION FOR ACCELERATOR DEVICES 有权
公开(公告)号：US20220368348A1
公开(公告)日：2022-11-17
申请号：US17870659
申请日：2022-07-21
申请人： INTEL CORPORATION
发明人： Laurent Coquerel , Fei Wang , John Browne , Smita Kumar , Declan Doherty , Marlow Weston , Reshma Pattan
IPC分类号： H03M7/30
摘要： An accelerator device determines a compression format based on a header of a structured data element to be decompressed. The accelerator device may configure the accelerator device based on the compression format. The accelerator device may decompress a data block of the structured data element based on the configuration.

8. 发明申请

US20160306416A1 Apparatus and Method for Adjusting Processor Power Usage Based On Network Load 审中-公开
标题翻译：基于网络负载调整处理器功耗的装置和方法
公开(公告)号：US20160306416A1
公开(公告)日：2016-10-20
申请号：US14688019
申请日：2015-04-16
申请人： Intel Corporation
发明人： John Browne , Chris Macnamara
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3209 , G06F1/3228 , G06F1/3243 , G06F9/4893 , G06F2209/548 , Y02D10/152 , Y02D10/24 , Y02D50/20
摘要： In an embodiment, a system includes a processor that includes a plurality of cores and a plurality of queue. Each queue includes storage locations to store packets to be processed by at least one of the cores. Each queue has a corresponding state that is one of active and inactive. Each active queue is enabled to store an incoming packet, and each inactive queue is disabled from storage of the incoming packet. Each queue has a corresponding queue depth that includes a count of occupied storage locations of the queue. The system also includes packet distribution logic to determine whether to change the state of a first queue of the plurality of queues from a first state to a second state based on a total queue depth that includes a sum of the queue depths of the active queues. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统包括包括多个核心和多个队列的处理器。每个队列包括用于存储要被至少一个核心处理的分组的存储位置。每个队列都有一个对应的状态，它是一个活动和非活动状态。启用每个活动队列以存储传入的数据包，并且禁止每个不活动队列存储进入的数据包。每个队列具有对应的队列深度，其包括队列占用的存储位置的计数。该系统还包括分组分配逻辑，用于基于包括活动队列的队列深度的总和的总队列深度来确定是否将多个队列中的第一队列的状态从第一状态改变到第二状态。描述和要求保护其他实施例。

9. 发明授权

US11630693B2 Technologies for power-aware scheduling for network packet processing 有权
公开(公告)号：US11630693B2
公开(公告)日：2023-04-18
申请号：US15951650
申请日：2018-04-12
申请人： Intel Corporation
发明人： John Browne , Chris MacNamara , Tomasz Kantecki , Peter McCarthy , Liang Ma , Mairtin O'Loingsigh , Rory Sexton , John Griffin , Nemanja Marjanovic , David Hunt
IPC分类号： G06F9/46 , G06F9/48 , H04L47/24 , G06F1/329 , H04L9/40 , H04L47/6275 , G06F1/3209 , G06F1/3296 , G06F1/3234 , H04L47/625 , G06F9/50 , G06F21/60
摘要： Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.

10. 发明申请

US20190041957A1 TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS 审中-公开
公开(公告)号：US20190041957A1
公开(公告)日：2019-02-07
申请号：US15951391
申请日：2018-04-12
申请人： Intel Corporation
发明人： David Hunt , Niall Power , Kevin Devey , Changzheng Wei , Bruce Richardson , Eliezer Tamir , Andrew Cunningham , Chris MacNamara , Nemanja Marjanovic , Rory Sexton , John Browne
IPC分类号： G06F1/32
摘要： Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

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