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1. 发明授权

US10811595B2 Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory 有权
公开(公告)号：US10811595B2
公开(公告)日：2020-10-20
申请号：US16073687
申请日：2016-04-01
申请人： INTEL CORPORATION
发明人： Kevin J. Lee , Oleg Golonzka , Tahir Ghani , Ruth A. Brain , Yih Wang
IPC分类号： H01L43/02 , H01L27/22 , H01L43/12 , H01L43/08 , H01L43/10 , H01L43/14
摘要： Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

2. 发明授权

US10224309B2 Integrated circuit die having backside passive components and methods associated therewith 有权
公开(公告)号：US10224309B2
公开(公告)日：2019-03-05
申请号：US15503377
申请日：2014-09-26
申请人： Intel Corporation
发明人： Kevin J. Lee
IPC分类号： H01L25/065 , H01L23/48 , H01L23/522 , H01L23/532 , H01L25/00 , H01L49/02 , H01L23/14 , H01L23/525
摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.

3. 发明授权

US11469268B2 Damascene-based approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures 有权
公开(公告)号：US11469268B2
公开(公告)日：2022-10-11
申请号：US16067803
申请日：2016-03-18
申请人： Intel Corporation
发明人： Kevin J. Lee , Yih Wang
IPC分类号： H01L27/22 , G11C11/16 , H01L43/06 , H01F41/34 , H01L23/528 , H01L43/04 , H01L43/14 , H01L43/12 , H01F10/32 , H01L21/8234 , H01L29/78
摘要： Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.

4. 发明申请

US20170358740A1 Logic Chip Including Embedded Magnetic Tunnel Junctions 审中-公开
公开(公告)号：US20170358740A1
公开(公告)日：2017-12-14
申请号：US15596650
申请日：2017-05-16
申请人： Intel Corporation
发明人： Kevin J. Lee , Tahir Ghani , Joseph M. Steigerwald , John H. Epple , Yih Wang
IPC分类号： H01L43/12 , H01L27/22 , H01L43/08
CPC分类号： H01L27/222 , G11C11/161 , H01L43/08 , H01L43/12
摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

5. 发明申请

US20150364425A1 3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED WITH FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES FABRICATED USING A DUAL DAMASCENE TYPE APPROACH 有权
标题翻译：三维互连结构，包括通过双金刚石类型方法制成的精细垂直金属重新分配线组合的通过硅的六角形
公开(公告)号：US20150364425A1
公开(公告)日：2015-12-17
申请号：US14836828
申请日：2015-08-26
申请人： Intel Corporation
发明人： Kevin J. Lee , Mark T. BOHR , Andrew W. YEOH , Christopher M. PELTO , Hiten KOTHARI , Seshu V. SATTIRAJU , Hang-Shing MA
IPC分类号： H01L23/538 , H01L23/29 , H01L23/528 , H01L23/00 , H01L23/31
CPC分类号： H01L23/5384 , H01L21/6835 , H01L21/76807 , H01L21/76898 , H01L23/291 , H01L23/3171 , H01L23/481 , H01L23/522 , H01L23/5286 , H01L23/5386 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/17 , H01L2221/6835 , H01L2224/0235 , H01L2224/02372 , H01L2224/02375 , H01L2224/024 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05664 , H01L2224/11002 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/14131 , H01L2224/16145 , H01L2224/16225 , H01L2224/17106 , H01L2924/00014 , H01L2924/13091 , H01L2924/1434 , H01L2924/1461 , H01L2924/186 , H01L2924/381 , H01L2924/01015 , H01L2924/01074 , H01L2924/01029 , H01L2924/0105 , H01L2924/01047 , H01L2924/00 , H01L2224/05552
摘要： A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
摘要翻译：描述了3D互连结构和制造方法，其中使用双镶嵌型工艺流程形成穿硅通孔（TSV）和金属再分布层（RDL）。氮化硅或碳化硅钝化层可以设置在减薄的器件晶片背面和RDL之间，以在工艺流程期间提供气密屏障和蚀刻停止层。

6. 发明授权

US09041146B2 Logic chip including embedded magnetic tunnel junctions 有权
标题翻译：逻辑芯片包括嵌入式磁隧道结
公开(公告)号：US09041146B2
公开(公告)日：2015-05-26
申请号：US13994716
申请日：2013-03-15
申请人： Intel Corporation
发明人： Kevin J. Lee , Tahir Ghani , Joseph M. Steigerwald , John H. Epple , Yih Wang
IPC分类号： H01L43/02 , H01L43/12 , H01L43/08 , H01L27/22
CPC分类号： H01L43/12 , G11C11/161 , H01L27/222 , H01L27/226 , H01L43/08
摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.
摘要翻译：实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上部MTJ层，较低MTJ层和直接接触上层MTJ层和下层MTJ层的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。在一个实施例中，第一和第二ILD直接彼此接触。本文描述了其它实施例。

7. 发明申请

US20150137368A1 LANDING STRUCTURE FOR THROUGH-SILICON VIA 审中-公开
标题翻译：通过硅的接地结构
公开(公告)号：US20150137368A1
公开(公告)日：2015-05-21
申请号：US14563926
申请日：2014-12-08
申请人： Intel Corporation
发明人： Christopher M. Pelto , Ruth A. Brain , Kevin J. Lee , Gerald S. Leatherman
IPC分类号： H01L23/48 , H01L21/768 , H01L23/522
CPC分类号： H01L23/481 , H01L21/76879 , H01L21/76898 , H01L23/522 , H01L23/5226 , H01L2224/16225 , H01L2924/15311
摘要： Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In one embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述与使用互连层的互连结构形成用于穿硅通孔（TSV）的着陆结构相关联的技术和配置。在一个实施例中，一种装置包括具有第一表面和与第一表面相对的第二表面的半导体衬底，设置在半导体衬底的第一表面上的器件层，器件层包括一个或多个晶体管器件，布置的互连层在所述器件层上，所述互连层包括多个互连结构以及设置在所述第一表面和所述第二表面之间的一个或多个穿硅通孔，其中所述多个互连结构包括互连结构，所述互连结构与所述一个或多个 TSV并且被配置为提供一个或多个TSV的一个或多个相应的着陆结构。可以描述和/或要求保护其他实施例。

8. 发明授权

US10290598B2 Method and apparatus for forming backside die planar devices and saw filter 有权
公开(公告)号：US10290598B2
公开(公告)日：2019-05-14
申请号：US15323521
申请日：2014-08-07
申请人： Intel Corporation
发明人： Kevin J. Lee , Ruchir Saraswat , Uwe Zillmann , Nicholas P. Cowley , Richard J. Goldman
IPC分类号： H01L23/00 , H01F27/28 , G06F1/16 , H01L23/64 , H01L23/522 , H03H9/64 , H03H7/42 , H01L23/48 , H01L23/66 , H01L23/525
摘要： Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

9. 发明授权

US09997563B2 Logic chip including embedded magnetic tunnel junctions 有权
公开(公告)号：US09997563B2
公开(公告)日：2018-06-12
申请号：US15596650
申请日：2017-05-16
申请人： Intel Corporation
发明人： Kevin J. Lee , Tahir Ghani , Joseph M. Steigerwald , John H. Epple , Yih Wang
IPC分类号： H01L27/22 , H01L43/12 , H01L43/08
CPC分类号： H01L27/222 , G11C11/161 , H01L43/08 , H01L43/12
摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

10. 发明申请

US20170245035A1 DIE WITH INTEGRATED MICROPHONE DEVICE USING THROUGH-SILICON VIAS (TSVs) 审中-公开
公开(公告)号：US20170245035A1
公开(公告)日：2017-08-24
申请号：US15502495
申请日：2014-09-17
申请人： Intel Corporation
发明人： Kevin J. Lee , Ruchir Saraswat , Uwe Zillmann , Valluri Bob Rao , Tor Lund-Larsen , Nicholas P. Cowley
IPC分类号： H04R1/04 , H01L23/48 , H04R19/04 , B81C1/00 , H04R1/40 , H04R19/00 , B81B7/02 , H01L21/768
CPC分类号： H04R1/04 , B81B7/02 , B81B2201/0257 , B81B2207/096 , B81C1/00158 , B81C2201/0132 , B81C2203/0109 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/481 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/131 , H01L2224/16227 , H01L2224/27002 , H01L2224/27618 , H01L2224/27848 , H01L2224/29011 , H01L2224/2919 , H01L2224/3201 , H01L2224/32058 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/83005 , H01L2224/83193 , H01L2224/83438 , H01L2224/8346 , H01L2224/83488 , H01L2224/8359 , H01L2224/83688 , H01L2224/83862 , H01L2224/92 , H01L2224/9222 , H01L2224/92225 , H01L2924/1461 , H01L2924/15311 , H01L2924/161 , H01L2924/16151 , H01L2924/16152 , H01L2924/163 , H01L2924/166 , H04R1/406 , H04R19/005 , H04R19/04 , H01L2924/014 , H01L2924/0665 , H01L2924/01014 , H01L2924/00014 , H01L2924/00012 , H01L2224/11 , H01L2224/27 , H01L2224/83 , H01L2224/81 , H01L2221/68304
摘要： Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

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