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1. 发明申请

US20220222183A1 TAGLESS IMPLICIT INTEGRITY WITH MULTI-PERSPECTIVE PATTERN SEARCH 有权
公开(公告)号：US20220222183A1
公开(公告)日：2022-07-14
申请号：US17704771
申请日：2022-03-25
申请人： Intel Corporation
发明人： David M. Durham , Michael Lemay
IPC分类号： G06F12/14 , G06F9/30
摘要： Embodiments are directed to tagless implicit integrity with multi-perspective pattern search for memory safety. An embodiment of an apparatus includes one or more processors comprising hardware circuitry to: access encrypted data stored in a memory hierarchy using a pointer; decrypt the encrypted data using a current version of a pointer tag of the pointer to yield first decrypted data; perform an entropy test on the first decrypted data; responsive to the entropy test failing to detect patterns in the first decrypted data, re-decrypt the encrypted data using one or more different versions of the pointer tag of the pointer to yield one or more other decrypted data; perform the entropy test on the one or more other decrypted versions; and responsive to the entropy test detecting the patterns in the one or more other decrypted data, signal an exception to the one or more processors with respect to the encrypted data.

2. 发明授权

US11360876B2 Apparatus and method for pausing processor trace for efficient analysis 有权
公开(公告)号：US11360876B2
公开(公告)日：2022-06-14
申请号：US16845512
申请日：2020-04-10
申请人： Intel Corporation
发明人： Michael Lemay , Beeman Strong
IPC分类号： G06F11/34 , G06F11/30 , G06F21/57 , G06F21/56
摘要： Processor trace systems and methods are described. For example, one embodiment comprises executing instrumented code by a compiler, the instrumented code including at least one call to un-instrumented code. The compiler can determine the at least one call to un-instrumented code is a next call to be executed. A resume tracing instruction can be inserted into the instrumented code prior to the at least one call to the un-instrumented code. The resume tracing instruction can be executed to selectively add processor tracing to the at least one call to the un-instrumented code, and the at least one call to the un-instrumented code can be executed.

3. 发明申请

US20210263779A1 FUNCTION AS A SERVICE (FAAS) SYSTEM ENHANCEMENTS 有权
公开(公告)号：US20210263779A1
公开(公告)日：2021-08-26
申请号：US17255588
申请日：2019-04-16
申请人： Intel Corporation
发明人： Mohammad R. Haghighat , Kshitij Doshi , Andrew J. Herdrich , Anup Mohan , Ravishankar R. Iyer , Mingqiu Sun , Krishna Bhuyan , Teck Joo Goh , Mohan J. Kumar , Michael Prinke , Michael Lemay , Leeor Peled , Jr-Shian Tsai , David M. Durham , Jeffrey D. Chamberlain , Vadim A. Sukhomlinov , Eric J. Dahlen , Sara Baghsorkhi , Harshad Sane , Areg Melik-Adamyan , Ravi Sahita , Dmitry Yurievich Babokin , Ian M. Steiner , Alexander Bachmutsky , Anil Rao , Mingwei Zhang , Nilesh K. Jain , Amin Firoozshahian , Baiju V. Patel , Wenyong Huang , Yeluri Raghuram
IPC分类号： G06F9/50 , G06F21/53 , G06F9/52 , G06F21/60 , G06F11/30 , G06F11/34
摘要： Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

4. 发明授权

US10795997B2 Hardened safe stack for return oriented programming attack mitigation 有权
公开(公告)号：US10795997B2
公开(公告)日：2020-10-06
申请号：US15629458
申请日：2017-06-21
申请人： INTEL CORPORATION
发明人： Michael Lemay
IPC分类号： G06F21/56 , G06F21/55 , G06F21/52 , G06F21/54
摘要： Techniques and computing devices for mitigating return-oriented programming (ROP) attacks are described. A hardened stack and an unhardened stack are provided. The hardened stack can include indications of return addresses while the unhardened stack can include all other memory allocations. A stack hardening instruction can be inserted before unhardened instructions (e.g., instructions that are themselves not authorized to access the hardened stack). The stack hardening instruction determines whether the unhardened instruction accessed memory outside the unhardened stack and generates a fault based on the determination. A register can be provided to include an indication of an address span of the unsafe stack. The stack hardening instruction can determine whether the unhardened instruction accessed a memory location outside the address range specified in the register and generate a fault accordingly.

5. 发明授权

US10558582B2 Technologies for execute only transactional memory 有权
公开(公告)号：US10558582B2
公开(公告)日：2020-02-11
申请号：US14974972
申请日：2015-12-18
申请人： Intel Corporation
发明人： David M. Durham , Michael Lemay , Men Long
IPC分类号： G06F12/00 , G06F12/1027 , G06F9/30 , G06F12/14
摘要： Technologies for execute only transactional memory include a computing device with a processor and a memory. The processor includes an instruction translation lookaside buffer (iTLB) and a data translation lookaside buffer (dTLB). In response to a page miss, the processor determines whether a page physical address is within an execute only transactional (XOT) range of the memory. If within the XOT range, the processor may populate the iTLB with the page physical address and prevent the dTLB from being populated with the page physical address. In response to an asynchronous change of control flow such as an interrupt, the processor determines whether a last iTLB translation is within the XOT range. If within the XOT range, the processor clears or otherwise secures the processor register state. The processor ensures that an XOT range starts execution at an authorized entry point. Other embodiments are described and claimed.

6. 发明授权

US10152612B2 Cryptographic operations for secure page mapping in a virtual machine environment 有权
公开(公告)号：US10152612B2
公开(公告)日：2018-12-11
申请号：US14866211
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： Michael Lemay
IPC分类号： G06F9/32 , G06F9/455 , H04L9/32 , G06F21/72 , G06F21/79
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for secure memory page mapping in a virtual machine (VM) environment. The system may include a processor configured to execute a virtual machine monitor (VMM). The VMM may be configured to maintain a table of cryptographic keys and associate a token with one of the memory pages to be mapped from a guest linear address (GLA) to a guest physical address (GPA). The token may include a key identifier (key ID) associated with one of the cryptographic keys, and an authentication code based on the GLA, the GPA, and one of the cryptographic keys. The system may also include a page walk processor configured to validate the token to indicate that the memory page associated with the token is authorized to be mapped from the GLA to the GPA.

7. 发明授权

US10061918B2 System, apparatus and method for filtering memory access logging in a processor 有权
公开(公告)号：US10061918B2
公开(公告)日：2018-08-28
申请号：US15088318
申请日：2016-04-01
申请人： Intel Corporation
发明人： Salmin Sultana , David M. Durham , Michael Lemay , Karanvir S. Grewal , Ravi L. Sahita
IPC分类号： G06F12/14 , G06F21/55 , G06F17/30 , G06F12/1009 , G06F21/56 , G06F9/455
CPC分类号： G06F21/552 , G06F12/1009 , G06F12/109 , G06F12/145 , G06F16/245 , G06F21/55 , G06F21/56 , G06F2009/45583 , G06F2009/45591 , G06F2212/1052 , G06F2212/151 , G06F2212/65 , G06F2212/657 , G06F2221/034
摘要： In one embodiment, a processor comprises: a first storage including a plurality of entries to store an address of a portion of a memory in which information has been modified; a second storage to store an identifier of a process for which information is to be stored into the first storage; and a first logic to identify a modification to a first portion of the memory and store a first address of the first portion of the memory in a first entry of the first storage, responsive to a determination that a current identifier of a current process corresponds to the identifier stored in the second storage. Other embodiments are described and claimed.

8. 发明授权

US11531750B2 Installing and manipulating a secure virtual machine image through an untrusted hypervisor 有权
公开(公告)号：US11531750B2
公开(公告)日：2022-12-20
申请号：US16937155
申请日：2020-07-23
申请人： Intel Corporation
发明人： David M. Durham , Karanvir S. Grewal , Sergej Deutsch , Michael Lemay
IPC分类号： G06F9/455 , G06F21/53 , G06F21/57 , H04L9/40
摘要： Systems, apparatuses and methods may provide for technology that associates a key domain of a plurality of key domains with a customer boot image, receives the customer boot image from the customer, and verifies the integrity of the customer boot image that is to be securely installed at memory locations determined from an untrusted privileged entity (e.g., a virtual machine manager).

9. 发明授权

US11409662B2 Apparatus and method for efficient process-based compartmentalization 有权
公开(公告)号：US11409662B2
公开(公告)日：2022-08-09
申请号：US17321087
申请日：2021-05-14
申请人： Intel Corporation
发明人： David M. Durham , Jacob Doweck , Michael Lemay , Deepak Gupta
IPC分类号： G06F12/10 , G06F12/1027
摘要： An apparatus and method for efficient process-based compartmentalization. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data; memory management circuitry coupled to the execution circuitry, the memory management circuitry to manage access to a system memory by a plurality of related processes using one or more process-specific translation structures and one or more shared translation structures to be shared by the related processes; and one or more control registers to store a process-specific base address pointer associated with a first process of the plurality of related processes and to store a shared base address pointer to identify the shared translation structures; wherein the memory management circuitry is to use the process-specific base address pointer in combination with a first linear address provided by the first process to walk the process-specific translation structures to identify any permissions and/or physical address associated with the first linear address, wherein if permissions are identified, the memory management circuitry is to use the permissions in place of any permissions specified in the shared translation structures.

10. 发明申请

US20220214879A1 CAPABILITY-BASED STACK PROTECTION FOR SOFTWARE FAULT ISOLATION 有权
公开(公告)号：US20220214879A1
公开(公告)日：2022-07-07
申请号：US17703121
申请日：2022-03-24
申请人： Intel Corporation
发明人： Michael Lemay , David M. Durham
IPC分类号： G06F9/30 , G06F9/50 , G06F21/60
摘要： Systems, methods, and apparatuses for generating a protected stack allocation pointer. In certain examples, a hardware processor core comprises a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising one or more fields to indicate a stack allocation index as an operand, and an opcode to indicate that an execution circuit is to generate a stack allocation pointer to reference an address in a stack and an address in a shadow stack; and an execution circuit to execute the decoded single instruction according to the opcode.

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