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    • 4. 发明授权
    • Accelerated interlane vector reduction instructions
    • 加速交错向量减少指令
    • US09588766B2
    • 2017-03-07
    • US13630154
    • 2012-09-28
    • Intel Corporation
    • Paul CaprioliAbhay S. KanhereJeffrey J. CookMuawya M. Al-Otoom
    • G06F12/00G06F7/38G06F9/00G06F9/44G06F9/30
    • G06F9/30036G06F9/30014G06F9/30032G06F9/3012G06F9/3887G06F9/3893
    • A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane.
    • 由处理器执行向量减少指令以对数据元素阵列提供有效的减少操作。 处理器包括向量寄存器。 每个向量寄存器被分成多个通道,每个通道存储相同数量的数据元素。 处理器还包括执行电路,其接收向量减少指令,以使用缩减运算符将存储在源操作数中的数据元素的阵列减少到目标操作数的结果。 源操作数和目标操作数中的每一个都是向量寄存器之一。 响应于向量减少指令,执行电路将减法运算符应用于每个通道中的两个数据元素,并且当存在每个通道中的至少一个数据元素时,移位一个或多个剩余数据元素。