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1. 发明申请

US20210359103A1 NANOSHEET TRANSISTOR WITH ASYMMETRIC GATE STACK 有权
公开(公告)号：US20210359103A1
公开(公告)日：2021-11-18
申请号：US16876443
申请日：2020-05-18
申请人： International Business Machines Corporation
发明人： Ruilong Xie , Carl Radens , Kangguo Cheng , JUNTAO LI , Dechao Guo , Tao Li , Tsung-Sheng Kang
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423 , H01L29/78
摘要： Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

2. 发明授权

US11176043B2 Distributed memory-augmented neural network architecture 有权
公开(公告)号：US11176043B2
公开(公告)日：2021-11-16
申请号：US16838294
申请日：2020-04-02
申请人： International Business Machines Corporation
发明人： Ahmet Serkan Ozcan , Tomasz Kornuta , Carl Radens , Nicolas Antoine
IPC分类号： G06F16/00 , G06F16/2453 , G06F12/02 , G06F12/00 , G06F12/08 , G06F3/06 , G06F12/0817 , G06N3/063 , G11C11/4093 , G11C11/4076 , G06F16/33 , G06F16/2458 , G06F12/06
摘要： A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

3. 发明授权

US10319630B2 Encapsulated damascene interconnect structure for integrated circuits 有权
公开(公告)号：US10319630B2
公开(公告)日：2019-06-11
申请号：US13629411
申请日：2012-09-27
申请人： STMicroelectronics, Inc. , International Business Machines Corporation
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
IPC分类号： H01L23/48 , H01L23/52 , H01L21/768 , H01L23/522 , H01L23/532
摘要： A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.

4. 发明申请

US20180144926A1 ADVANCED INTERCONNECT WITH AIR GAP 审中-公开
公开(公告)号：US20180144926A1
公开(公告)日：2018-05-24
申请号：US15874654
申请日：2018-01-18
申请人： STMicroelectronics, Inc. , International Business Machines Corporation
发明人： John H. Zhang , Yann Mignot , Lawrence A. Clevenger , Carl Radens , Richard Stephen Wise , Yiheng Xu , Yannick Loquet , Hsueh-Chung Chen
IPC分类号： H01L21/02 , H01L21/768 , H01L21/311 , H01L23/522 , H01L23/532
CPC分类号： H01L21/0217 , H01L21/31144 , H01L21/7682 , H01L21/76831 , H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

5. 发明申请

US20160218070A1 MULTILAYER STRUCTURE IN AN INTEGRATED CIRCUIT FOR DAMAGE PREVENTION AND DETECTION AND METHODS OF CREATING THE SAME 有权
标题翻译：用于损坏预防和检测的集成电路中的多层结构及其创建方法
公开(公告)号：US20160218070A1
公开(公告)日：2016-07-28
申请号：US15090996
申请日：2016-04-05
申请人： International Business Machines Corporation , STMicroelectronics, Inc.
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Byoung Youp Kim , Walter Kleemeier
IPC分类号： H01L23/00 , H01L21/66 , H01L23/532 , H01L21/768 , H01L23/528
CPC分类号： H01L23/562 , H01L21/76805 , H01L21/76843 , H01L21/76897 , H01L22/12 , H01L22/14 , H01L22/32 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/5228 , H01L23/528 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.
摘要翻译：各种实施例便于集成电路的管芯保护。在一个实施例中，多层结构形成在多个层次上并沿着模具的边缘，以防止和检测对模具的损坏。所述多层结构包括支撑层，覆盖所述支撑层的第一多个介电柱，填充所述第一多个介电柱之间的空间的金属层，覆盖所述第一多个介电柱和所述金属层的绝缘层，第二覆盖绝缘层的多个介电柱，以及填充第二多个介电柱之间的空间的第二金属层。

6. 发明授权

US09385177B2 Technique for fabrication of microelectronic capacitors and resistors 有权
标题翻译：微电子电容器和电阻器制造技术
公开(公告)号：US09385177B2
公开(公告)日：2016-07-05
申请号：US14068198
申请日：2013-10-31
申请人： STMicroelectronics, Inc. , International Business Machines Corporation
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Edem Wornyo
IPC分类号： H01L49/02 , H01L23/525 , H01L27/01 , H01L21/3105 , H01L23/522 , H01L21/321
CPC分类号： H01L27/016 , H01L21/31053 , H01L21/3212 , H01L23/5223 , H01L23/5228 , H01L23/5252 , H01L23/5256 , H01L28/20 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.
摘要翻译：半导体处理步骤的顺序允许在公共结构内形成垂直和水平的纳米级蛇形电阻器和平行板电容器。制造这种结构的方法巧妙地利用CMP工艺不均匀性，其中绝缘材料的CMP抛光速率根据某些基础形貌而变化。通过在绝缘材料层之下建立这样的形貌，可以通过利用差分抛光速率在不同的区域产生绝缘体的不同膜厚度，从而避免使用光刻掩模。在一个实施例中，使用仅需要两个掩模层的工艺，可以在公共介电块内形成多个电阻器和电容器作为紧凑的集成结构。这样形成为一组集成电路元件的电阻器和电容器分别适合用作微电子熔丝和反熔丝，以保护下面的微电子电路。

7. 发明申请

US20150279784A1 INTERCONNECT STRUCTURE HAVING LARGE SELF-ALIGNED VIAS 有权
标题翻译：具有大型自对准VIAS的互连结构
公开(公告)号：US20150279784A1
公开(公告)日：2015-10-01
申请号：US14231448
申请日：2014-03-31
申请人： International Business Machines Corporation , STMicroelectronics, Inc.
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Richard Stephen Wise , Terry Spooner , Nicole A. Saulnier
IPC分类号： H01L23/532 , G03F1/36 , H01L21/768
CPC分类号： G03F1/36 , G03F1/00 , H01L21/0274 , H01L21/31144 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.
摘要翻译：公开了一种容纳小金属线和大通孔的波浪线互连结构。用于图形金属线沟槽的光刻掩模设计使用光学邻近校正（OPC）技术来使用矩形不透明特征来近似波浪线。可以使用自对准双镶嵌工艺形成大通孔，而不需要单独的通孔光刻掩模。相反，牺牲层允许蚀刻下面的厚介质块，同时保护对应于金属线互连的沟槽的窄特征。所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。通过提升通孔的收缩约束，从而允许通孔覆盖区超过金属线宽度的最小尺寸，为另外的工艺世代清除了一条路径，以继续将金属线收缩到低于10nm的尺寸。

8. 发明授权

US09018092B2 Encapsulated metal interconnect 有权
标题翻译：封装金属互连
公开(公告)号：US09018092B2
公开(公告)日：2015-04-28
申请号：US13629402
申请日：2012-09-27
申请人： STMicroelectronics, Inc. , International Business Machines Corporation
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/768
CPC分类号： H01L21/76816 , H01L21/76807 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76897 , H01L23/5226 , H01L23/5283 , H01L23/53295
摘要： A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.
摘要翻译：多个金属轨道形成在集成电路管芯内，堆叠在管芯内的三个金属层。在中间金属层的金属轨道周围形成保护电介质层。保护性介电层用作硬掩模，以在中间金属层之上和之下的金属层中限定金属轨道之间的接触通孔。

9. 发明授权

US08900990B2 System and method of combining damascenes and subtract metal etch for advanced back end of line interconnections 有权
标题翻译：组合大马士革的系统和方法，并减去金属蚀刻用于线路互连的后端
公开(公告)号：US08900990B2
公开(公告)日：2014-12-02
申请号：US13731878
申请日：2012-12-31
申请人： STMicroelectronics, Inc. , International Business Machines Corporation
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Walter Kleemeier , Cindy Goldberg
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/768 , H01L23/538
CPC分类号： H01L23/5384 , H01L21/76807 , H01L21/7682 , H01L21/76883 , H01L21/76885 , H01L21/76897 , H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.
摘要翻译：金属互连通过组合镶嵌工艺和减去金属蚀刻形成在一体中。在电介质层中形成宽沟槽。导电材料沉积在宽沟槽中。在导电材料中蚀刻沟槽以描绘多个金属插塞，每个金属插头接触由宽沟槽暴露的相应金属轨道。

10. 发明申请

US20140175610A1 ELECTROSTATIC DISCHARGE DEVICES FOR INTEGRATED CIRCUITS 有权
标题翻译：用于集成电路的静电放电装置
公开(公告)号：US20140175610A1
公开(公告)日：2014-06-26
申请号：US13725666
申请日：2012-12-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , STMICROELECTRONICS, INC.
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
IPC分类号： H01L27/02 , H01L21/266
CPC分类号： H01L27/0248 , H01L21/26586 , H01L21/266 , H01L27/0255
摘要： A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts. Use of tilted implants in fabricating the junction diode array allows a single hard mask to be used to implant multiple ion species. Furthermore, a different implant tilt angle can be chosen for each species, along with other parameters, (e.g., implant energy, implant mask thickness, and dimensions of the mask openings) so as to craft the shape of the implanted regions. Isolation regions can be inserted between already formed diodes, using the same implant hard mask if desired. A buried oxide layer can be used to prevent diffusion of dopants into the substrate beyond a selected depth.
摘要翻译：可以制造用于保护集成电路免受静电放电的结二极管阵列，以包括各种尺寸的对称和/或非对称结二极管。二极管可以配置为通过未封装的触点提供低电压和电流放电，或通过封装的触点提供高电压和电流放电。在制造结二极管阵列中使用倾斜植入物允许使用单个硬掩模来植入多个离子物质。此外，可以为每个种类以及其他参数（例如，植入能量，植入物掩模厚度和掩模开口的尺寸）选择不同的植入物倾斜角度，以便制造植入区域的形状。如果需要，可以使用相同的植入物硬掩模，在已经形成的二极管之间插入隔离区域。可以使用掩埋氧化物层来防止掺杂剂扩散到超过选定深度的衬底中。

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