专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11526768B2 Real time cognitive reasoning using a circuit with varying confidence level alerts 有权
公开(公告)号：US11526768B2
公开(公告)日：2022-12-13
申请号：US15612272
申请日：2017-06-02
申请人： International Business Machines Corporation
发明人： Karl R. Erickson , Phil C. Paone , George F. Paulik , David P. Paulsen , John E. Sheets, II , Gregory J. Uhlmann
IPC分类号： G06J1/00 , G06N5/02 , G08B3/00 , G06F15/76
摘要： Real time cognitive reasoning using a circuit with varying confidence level alerts including receiving a first set of data results and a second set of data results; transferring a first unit of charge from a first charge capacitor on the A-B circuit to a collection capacitor on the A-B circuit for each of the first set of data results that indicates a positive data point; transferring a second unit of charge from a second charge capacitor to the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the A-B circuit if the charge on the collection capacitor exceeds a first charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance with a first confidence level.

2. 发明授权

US10663502B2 Real time cognitive monitoring of correlations between variables 有权
公开(公告)号：US10663502B2
公开(公告)日：2020-05-26
申请号：US15612433
申请日：2017-06-02
申请人： International Business Machines Corporation
发明人： Karl R. Erickson , Phil C. Paone , David P. Paulsen , George F. Paulik , Raymond A. Richetta , John E. Sheets, II , Gregory J. Uhlmann
IPC分类号： G01R27/26 , G01R29/24 , G06F7/02 , G06F7/00
摘要： Real time cognitive monitoring of correlations between variables including receiving, by a circuit, a first set of data results and a second set of data results, wherein each set of data results comprises binary data points; adding a unit of charge to a collection capacitor on the circuit for each of the first set of data results that indicates a positive data point; removing a unit of charge from the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the circuit if the charge on the collection capacitor exceeds a high charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance.

3. 发明授权

US10170578B2 Through-substrate via power gating and delivery bipolar transistor 有权
公开(公告)号：US10170578B2
公开(公告)日：2019-01-01
申请号：US15609814
申请日：2017-05-31
申请人： International Business Machines Corporation
发明人： Gerald K. Bartley , David P. Paulsen , John E. Sheets, II
IPC分类号： H01L29/66 , H01L23/00 , H01L29/08 , H01L29/73 , H01L29/732
摘要： Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through via can also include metal contacts to the collector, base, and emitter which enable the through to be coupled to a metal routing layer or a solder bump.

4. 发明授权

US10037792B1 Optimizing data approximation analysis using low power circuitry 有权
公开(公告)号：US10037792B1
公开(公告)日：2018-07-31
申请号：US15612316
申请日：2017-06-02
申请人： International Business Machines Corporation
发明人： Karl R. Erickson , Phil C. Paone , George F. Paulik , David P. Paulsen , John E. Sheets, II , Gregory J. Uhlmann
IPC分类号： G11C11/24 , G11C11/40
CPC分类号： G11C11/24 , G11C7/1084 , G11C7/1087 , G11C7/1093 , G11C11/40 , G11C29/021 , G11C29/028 , G11C29/50004 , G11C29/50008 , G11C2029/0403 , G11C2029/5004 , G11C2207/2254
摘要： Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.

5. 发明授权

US09589653B1 Creating default states for non-volatile memory elements 有权
标题翻译：为非易失性存储器元素创建默认状态
公开(公告)号：US09589653B1
公开(公告)日：2017-03-07
申请号：US15070499
申请日：2016-03-15
申请人： International Business Machines Corporation
发明人： Karl R. Erickson , Robert E. Kilker , Phil C. Paone , David P. Paulsen , Gregory J. Uhlmann
IPC分类号： G11C11/34 , G11C16/24 , G11C16/10 , G11C16/26
CPC分类号： G11C16/26 , G11C16/08 , G11C16/10
摘要： A circuit has a wordline with an NVM element utilizing a first FET coupled to bitline true and a second FET coupled to bitline complement. A NFET coupled to the bitline complement is configured to pull bitline true toward ground in response to bitline complement reaching a first voltage. One or more wordline drivers are coupled to the NVM element such that a first path from a wordline driver is coupled to the first FET while a second path from a wordline driver is coupled to the second FET. The first path is current-limited in comparison to the second path, such that a first slew rate between a wordline driver and the first FET is slower than a second slew rate between a wordline driver and the second FET. The slew rate disparity allows the bitline complement to reach the first voltage.
摘要翻译：电路具有一个字线，其中NVM元件利用耦合到位线的第一FET和耦合到位线补码的第二FET。耦合到位线补码的NFET被配置为响应于位线补码达到第一电压而将位线真向地拉。一个或多个字线驱动器耦合到NVM元件，使得来自字线驱动器的第一路径耦合到第一FET，而来自字线驱动器的第二路径耦合到第二FET。与第二路径相比，第一路径是电流限制的，使得字线驱动器和第一FET之间的第一转换速率比字线驱动器和第二FET之间的第二转换速率慢。转换速率差异允许位线补码达到第一个电压。

6. 发明授权

US09252083B2 Semiconductor chip with power gating through silicon vias 有权
公开(公告)号：US09252083B2
公开(公告)日：2016-02-02
申请号：US14618106
申请日：2015-02-10
申请人： International Business Machines Corporation
发明人： Karl R. Erickson , Phil C. Paone , David P. Paulsen , John E. Sheets, II , Gregory J. Uhlmann , Kelly L. Williams
IPC分类号： H01L23/48 , H01L27/112 , H01L23/525 , H01L21/74 , H01L21/66 , H01L23/00
CPC分类号： H01L23/481 , H01L21/743 , H01L22/32 , H01L23/5252 , H01L24/13 , H01L27/11206 , H01L2224/13025
摘要： A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.

7. 发明申请

US20150228757A1 SIDE GATE ASSIST IN METAL GATE FIRST PROCESS 有权
标题翻译：金属门第一工序中的侧门辅助
公开(公告)号：US20150228757A1
公开(公告)日：2015-08-13
申请号：US14178511
申请日：2014-02-12
申请人： International Business Machines Corporation
发明人： Karl R. Erickson , Phil C. Paone , David P. Paulsen , John E. Sheets, II , Gregory J. Uhlmann , Kelly L. Williams
IPC分类号： H01L29/66 , H01L29/423 , H01L21/28
CPC分类号： H01L29/66484 , H01L21/28035 , H01L29/165 , H01L29/4238 , H01L29/4983 , H01L29/6659 , H01L29/7833
摘要： A method of making a semiconductor device in a gate first process with side gate assists. A first gate may be formed within a gate region. The first gate may include a first gate conductor separated from a semiconductor substrate by a first insulator disposed between the first gate conductor and the semiconductor substrate. A second gate may be formed within the gate region. The second gate may include a second gate conductor separated from a vertical surface of the first gate conductor and the semiconductor substrate by a second insulator. A first electrical contact and a second electrical contact may be formed. The first and second electrical contacts may be disposed on opposite ends of the gate region for respectively connecting the first gate conductor and the second gate conductor to a respective voltage.
摘要翻译：在具有侧门辅助的门第一处理中制造半导体器件的方法。第一栅极可以形成在栅极区域内。第一栅极可以包括通过布置在第一栅极导体和半导体衬底之间的第一绝缘体与半导体衬底分离的第一栅极导体。第二栅极可以形成在栅极区域内。第二栅极可以包括通过第二绝缘体与第一栅极导体和半导体衬底的垂直表面分离的第二栅极导体。可以形成第一电接触和第二电接触。第一和第二电触点可以设置在栅极区域的相对端上，用于将第一栅极导体和第二栅极导体分别连接到相应的电压。

8. 发明授权

US09021407B2 Signal path of a multiple-patterned semiconductor device 有权
公开(公告)号：US09021407B2
公开(公告)日：2015-04-28
申请号：US13787948
申请日：2013-03-07
申请人： International Business Machines Corporation
发明人： David H. Allen , Douglas M. Dewanz , David P. Paulsen , John E. Sheets, II
IPC分类号： G06F17/50 , G03F1/00 , H01L21/033 , H01L27/02 , H01L23/528
CPC分类号： H01L21/0337 , H01L23/5286 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal.

9. 发明申请

US20150076615A1 INTERDIGITATED FINFETS 有权
公开(公告)号：US20150076615A1
公开(公告)日：2015-03-19
申请号：US14031202
申请日：2013-09-19
申请人： International Business Machines Corporation
发明人： Karl R. Erickson , Phil C. Paone , David P. Paulsen , John E. Sheets, II , Gregory J. Uhlmann , Kelly L. Williams
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/823821 , H01L29/66803
摘要： A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer.
摘要翻译：半导体器件包括从半导体基底上升出的第一鳍片。它还包括从半导体基地升起的第二个鳍。第二翅片基本上平行于在第一翅片和第二翅片之间形成跨距的第一翅片。第一电介质层沉积在第一鳍片的第一栅极主体区域，第二鳍片的第二栅极主体区域和半导体基底的相邻表面的暴露表面上，该相邻表面限定第一和第二栅极体区域之间的跨距。栅极电极层被夹在第一电介质层和第二电介质层之间。半导体器件包括在跨度内在第一鳍片和第二鳍片之间交错的第三鳍片。第三鳍片的门体区域的露出面与第二电介质层接触。

10. 发明申请

US20150011023A1 MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20150011023A1
公开(公告)日：2015-01-08
申请号：US14268606
申请日：2014-05-02
申请人： International Business Machines Corporation
发明人： David H. Allen , Douglas M. Dewanz , David P. Paulsen , John E. Sheets, II
IPC分类号： H01L21/66 , H01L21/768
CPC分类号： H01L21/76838 , H01L21/76816 , H01L22/12 , H01L22/20 , H01L22/26 , H01L23/48 , H01L23/5225 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes a conductive layer. The conductive layer includes conductive tracks which may be defined by photomasks. The conductive tracks may have quality characteristics. Distinct quality characteristics of distinct conductive tracks may be compared. Based on the comparison, signals and supply voltage may be routed on particular conductive tracks.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式