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1. 发明授权

US09858188B2 Adaptively enabling and disabling snooping fastpath commands 有权
公开(公告)号：US09858188B2
公开(公告)日：2018-01-02
申请号：US14733665
申请日：2015-06-08
申请人： International Business Machines Corporation
发明人： Guy L. Guthrie , Hien M. Le , Hugh Shen , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/0831 , G06F12/0862
CPC分类号： G06F12/0831 , G06F12/0862 , G06F2212/621 , Y02D10/13
摘要： Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.

2. 发明授权

US09372797B2 Adaptively enabling and disabling snooping fastpath commands 有权
标题翻译：适应性地启用和禁用snooping fastpath命令
公开(公告)号：US09372797B2
公开(公告)日：2016-06-21
申请号：US14176775
申请日：2014-02-10
申请人： International Business Machines Corporation
发明人： Guy L. Guthrie , Hien M. Le , Hugh Shen , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0862 , G06F2212/621 , Y02D10/13
摘要： Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.
摘要翻译：统计数据用于在处理器的总线上启用或禁用窥探。通过第一总线或第二总线接收命令，该第一总线或第二总线在处理器上可通信地耦合处理器核和高速缓存。小命令上的缓存逻辑确定小节上的本地缓存是否能够满足命令中指定的数据请求。响应于确定本地高速缓存能够满足对数据的请求，高速缓存逻辑更新维护在该小区上的统计数据。统计数据表示本地缓存可以满足将来的数据请求的概率。至少部分地基于统计数据，高速缓存逻辑确定是否在本地高速缓存上启用或禁用第二总线上的窥探。

3. 发明授权

US09058195B2 Virtual machines failover 有权
标题翻译：虚拟机故障切换
公开(公告)号：US09058195B2
公开(公告)日：2015-06-16
申请号：US13778802
申请日：2013-02-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sanjeev Ghai , Guy L. Guthrie , Geraint North , William J. Starke , Phillip G. Williams
IPC分类号： G06F12/12 , G06F9/455 , G06F12/08 , G06F11/00
CPC分类号： G06F9/45533 , G06F9/45558 , G06F11/00 , G06F11/1484 , G06F11/202 , G06F11/2041 , G06F11/2097 , G06F12/0891 , G06F2009/45583
摘要： Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache comprising a plurality of cache rows (1210), each cache row comprising a cache line (1214) and an image modification flag (1217) indicating a modification of said cache line caused by the running of the virtual machine; and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit comprises a replication manager adapted to define a log (200) in the memory prior to running the virtual machine in said first operating mode; and said cache further includes a cache controller (122) adapted to periodically check said image modification flags; write only the memory address of the flagged cache lines in the defined log and subsequently clear the image modification flags. A computer cluster including such computer systems and a method of managing such a computer cluster are also disclosed.
摘要翻译：公开了一种包括适于以第一操作模式运行虚拟机的处理器单元（110）的计算机系统（100）所述高速缓存包括多个高速缓存行（1210），每个高速缓存行包括高速缓存行（1214）和指示所述高速缓存行的修改的图像修改标志（1217），所述高速缓存行指示由虚拟机的运行; 以及高速缓存控制器可访问的存储器（140），用于存储所述虚拟机的图像; 其中所述处理器单元包括适于在所述第一操作模式中运行所述虚拟机之前在所述存储器中定义日志（200）的复制管理器; 并且所述高速缓存还包括适于周期性地检查所述图像修改标志的高速缓存控制器（122）只写入定义的日志中标记的高速缓存行的存储器地址，然后清除映像修改标志。还公开了包括这样的计算机系统的计算机集群和管理这种计算机集群的方法。

4. 发明授权

US10467008B2 Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor 有权
公开(公告)号：US10467008B2
公开(公告)日：2019-11-05
申请号：US15168560
申请日：2016-05-31
申请人： International Business Machines Corporation
发明人： David S. Levitan , Mehul Patel , Albert J. Van Norstrand, Jr. , Phillip G. Williams
IPC分类号： G06F9/30 , G06F15/76 , G06F9/32 , G06F9/38
摘要： Methods and apparatus for identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor including receiving, by an instruction fetch unit of the processor, the interrupt ITAG; retrieving an effective address table (EAT) row from an EAT, wherein the EAT row comprises a range of EAs and a first ITAG of a range of ITAGs; accessing a processor instruction vector comprising a plurality of elements, each element corresponding to one of a plurality of ITAGs; applying a mask to the processor instruction vector to obtain a portion of the processor instruction vector that begins with an element corresponding to the first ITAG and is defined by an element corresponding to the interrupt ITAG; calculating an EA offset; and identifying the EA for the interrupt ITAG using the EA offset and the range of EAs in the retrieved EAT row.

5. 发明授权

US10387154B2 Thread migration using a microcode engine of a multi-slice processor 有权
公开(公告)号：US10387154B2
公开(公告)日：2019-08-20
申请号：US15069581
申请日：2016-03-14
申请人： International Business Machines Corporation
发明人： James W. Bishop , Marcy E. Byers , Steven R. Carlough , Paul M. Kennedy , Albert J. Van Norstrand, Jr. , Phillip G. Williams
IPC分类号： G06F9/30 , G06F9/38 , G06F13/40 , G06F13/42
摘要： Methods and apparatus for thread migration using a microcode engine of a multi-slice processor including issuing a thread migration instruction to the microcode engine of a decode unit, the thread migration instruction comprising an indication that the thread migration instruction is to be processed by the microcode engine; decoding, by the microcode engine, the thread migration instruction into a plurality of internal operations each targeting a different register entry; transmitting the plurality of internal operations to a dispatcher of the multi-slice processor; and manipulating, by the multi-slice processor, a plurality of register entries according to the plurality of internal operations.

6. 发明授权

US09529717B2 Preserving an invalid global domain indication when installing a shared cache line in a cache 有权
标题翻译：在缓存中安装共享缓存行时，保留无效的全局域指示
公开(公告)号：US09529717B2
公开(公告)日：2016-12-27
申请号：US14735272
申请日：2015-06-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hien Minh Le , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0828 , G06F12/0817 , G06F12/0831 , G06F12/0833 , G06F12/0864 , G06F12/0897 , G06F2212/314 , G06F2212/6032
摘要： A technique for operating a memory system for a node includes interrogating, by a cache, an associated cache directory to determine whether a shared cache line to be installed in the cache is associated with an invalid global state in the cache. The invalid global state specifies that a version of the shared cache line has been intervened off-node. In response to the shared cache line being in the invalid global state the cache spawns a castout invalid global command for the shared cache line. The shared cache line is installed in the cache. A coherence state for the shared cache line is updated in the associated cache directory to indicate the shared cache line is shared.
摘要翻译：用于操作用于节点的存储器系统的技术包括由高速缓存询问相关联的高速缓存目录，以确定要安装在高速缓存中的共享高速缓存行是否与高速缓存中的无效全局状态相关联。无效的全局状态指定共享高速缓存行的版本已经在节点之外插入。响应于共享高速缓存行处于无效全局状态，缓存为共享高速缓存行产生一个抛出无效的全局命令。共享缓存行安装在缓存中。在相关联的高速缓存目录中更新共享高速缓存行的一致性状态，以指示共享高速缓存行被共享。

7. 发明申请

US20150269076A1 ADAPTIVELY ENABLING AND DISABLING SNOOPING FASTPATH COMMANDS 有权
标题翻译：适应性地启用和禁用SNOOPING FASTPATH命令
公开(公告)号：US20150269076A1
公开(公告)日：2015-09-24
申请号：US14733665
申请日：2015-06-08
申请人： International Business Machines Corporation
发明人： Guy L. Guthrie , Hien M. Le , Hugh Shen , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0862 , G06F2212/621 , Y02D10/13
摘要： Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.
摘要翻译：统计数据用于在处理器的总线上启用或禁用窥探。通过第一总线或第二总线接收命令，该第一总线或第二总线在处理器上可通信地耦合处理器核和高速缓存。小命令上的缓存逻辑确定小节上的本地缓存是否能够满足命令中指定的数据请求。响应于确定本地高速缓存能够满足对数据的请求，高速缓存逻辑更新维护在该小区上的统计数据。统计数据表示本地缓存可以满足将来的数据请求的概率。至少部分地基于统计数据，高速缓存逻辑确定是否在本地高速缓存上启用或禁用第二总线上的窥探。

8. 发明授权

US08930629B2 Data cache block deallocate requests in a multi-level cache hierarchy 有权
标题翻译：数据缓存块在多级缓存层次结构中释放请求
公开(公告)号：US08930629B2
公开(公告)日：2015-01-06
申请号：US13655833
申请日：2012-10-19
申请人： International Business Machines Corporation
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0817 , G06F12/0804 , G06F12/121 , G06F12/122 , G06F12/126
摘要： In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.
摘要翻译：响应于执行取消分配指令，将指定目标高速缓存行的目标地址的解除分配请求从处理器核发送到较低级高速缓存。作为响应，确定目标地址是否在较低级别高速缓存中。如果是这样，则目标高速缓存行被保留在较低级高速缓存的数据阵列中，并且更新较低级高速缓存的替换顺序字段，使得目标高速缓存行更可能响应于后续高速缓存未命中而被驱逐在包含目标缓存行的同余类中。响应于随后的高速缓存未命中，目标高速缓存行被推出到较低级缓存，指示目标高速缓存行是处理器核心的先前释放请求的目标。

9. 发明授权

US11748104B2 Microprocessor that fuses load and compare instructions 有权
公开(公告)号：US11748104B2
公开(公告)日：2023-09-05
申请号：US16941969
申请日：2020-07-29
申请人： International Business Machines Corporation
发明人： Bryan Lloyd , David A. Hrusecky , Sundeep Chadha , Dung Q. Nguyen , Christian Gerhard Zoellin , Brian W. Thompto , Sheldon Bernard Levenstein , Phillip G. Williams
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/30021 , G06F9/30043 , G06F9/3802 , G06F9/3867
摘要： Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.

10. 发明申请

US20220035634A1 MICROPROCESSOR THAT FUSES LOAD AND COMPARE INSTRUCTIONS 有权
公开(公告)号：US20220035634A1
公开(公告)日：2022-02-03
申请号：US16941969
申请日：2020-07-29
申请人： International Business Machines Corporation
发明人： Bryan Lloyd , David A. Hrusecky , Sundeep Chadha , Dung Q. Nguyen , Christian Gerhard Zoellin , Brian W. Thompto , Sheldon Bernard Levenstein , Phillip G. Williams
IPC分类号： G06F9/30 , G06F9/38
摘要： Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.

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