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1. 发明申请

US20230133157A1 BACKSIDE METAL-INSULATOR-METAL (MIM) CAPACITORS 有权
公开(公告)号：US20230133157A1
公开(公告)日：2023-05-04
申请号：US17453516
申请日：2021-11-04
申请人： International Business Machines Corporation
发明人： Ruilong XIE , Takeshi NOGAMI , Roy R. YU , Balasubramanian PRANATHARTHIHARAN , Chih-Chao YANG
IPC分类号： H01L23/528 , H01L23/50 , H01L21/768 , H01L23/522 , H01L49/02
摘要： A method of fabricating a semiconductor device comprises forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer, forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench, and forming a first contact to a first metal layer of the plurality of layers. Forming the first contact comprises forming first recesses in a second metal layer of the plurality of layers, and filling the first recesses with an insulative material. The method further comprises forming a second contact to the second metal layer. Forming the second contact comprises forming second recesses in the first metal layer, and filling the second recesses with the insulative material.

2. 发明申请

US20230031574A1 MOON-SHAPED BOTTOM SPACER FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR (VTFET) DEVICES 有权
公开(公告)号：US20230031574A1
公开(公告)日：2023-02-02
申请号：US17388572
申请日：2021-07-29
申请人： International Business Machines Corporation
发明人： Ruilong XIE , Chen ZHANG , Julien FROUGIER , Alexander REZNICEK , Shogo MOCHIZUKI
IPC分类号： H01L29/78 , H01L29/417 , H01L29/66
摘要： A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

3. 发明申请

US20150349085A1 METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SIDEWALL SPACERS FOR CONFINING EPITAXIAL GROWTH 有权
标题翻译：用于制造具有边缘间隔的半导体器件用于限制外延生长的方法
公开(公告)号：US20150349085A1
公开(公告)日：2015-12-03
申请号：US14288766
申请日：2014-05-28
申请人： STMICROELECTRONICS, INC. , GLOBALFOUNDRIES Inc. , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Qing LIU , Ruilong XIE , Xiuyu CAI , Chun-chen YEH
IPC分类号： H01L29/66 , H01L29/165 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/02164 , H01L21/02178 , H01L21/0228 , H01L21/31105 , H01L21/823814 , H01L21/823821 , H01L27/0924 , H01L29/0847 , H01L29/1033 , H01L29/165 , H01L29/785 , H01L29/7851
摘要： A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.
摘要翻译：制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。去除该对侧壁间隔物之间的至少一个电介质层和半导体翅片的端部。源极/漏极区域形成在该对侧壁间隔物之间。

4. 发明申请

US20140353734A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION WITH REDUCED GATE AND CONTACT RESISTANCES 有权
标题翻译：半导体器件和制造方法与减少门和接触电阻
公开(公告)号：US20140353734A1
公开(公告)日：2014-12-04
申请号：US13909328
申请日：2013-06-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc.
发明人： Ruilong XIE , Xiuyu CAI , Vimal KAMINENI , Kangguo CHENG , Ali KHAKIFIROOZ
IPC分类号： H01L21/28 , H01L29/417 , H01L29/423 , H01L21/283
CPC分类号： H01L29/42376 , H01L21/28088 , H01L21/28114 , H01L21/283 , H01L21/76834 , H01L21/76843 , H01L21/76885 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L23/53266 , H01L29/41775 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures with reduced gate and/or contact resistances and fabrication methods are provided. The method includes: providing a semiconductor device, which includes forming a transistor of the semiconductor device, where the transistor forming includes: forming a T-shaped gate for the transistor, the T-shaped gate being T-shaped in elevational cross-section; and forming an inverted-T-shaped contact to an active region of the transistor, the inverted-T-shaped contact including a conductive structure with an inverted T-shape in elevational cross-section.
摘要翻译：提供具有减小的栅极和/或接触电阻的半导体结构和制造方法。该方法包括：提供半导体器件，其包括形成半导体器件的晶体管，其中晶体管形成包括：形成用于晶体管的T形栅极，T形栅极呈垂直截面为T形; 并且在晶体管的有源区域形成倒T形的接触，所述倒T形接触件包括在横截面上具有倒T形的导电结构。

5. 发明申请

US20140299924A1 FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE 有权
标题翻译：形成替代盖结构的电介质层
公开(公告)号：US20140299924A1
公开(公告)日：2014-10-09
申请号：US14285852
申请日：2014-05-23
申请人： GLOBALFOUNFRIES SINGAPORE PTE. LTD. , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ruilong XIE , Balasubramanian PRANATHARTHI HARAN , David V. HORAK , Su Chen FAN
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/42376 , H01L21/28088 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.
摘要翻译：通过在更换的栅极结构中形成电介质盖来减少接触短路的栅极。实施例包括在衬底上形成替代的栅极结构，所述替换的栅极结构包括具有空腔的ILD，在ILD的顶表面上的第一金属和衬里的空腔，以及在第一金属上填充空腔的第二金属，平面化第一和第二金属，在第二金属上形成氧化物，去除氧化物，使空腔中的第一和第二金属凹陷，形成凹陷，并用电介质材料填充凹槽。实施例还包括具有垂直侧壁，梯形形状，T形或Y形的电介质盖。

6. 发明申请

US20230093101A1 BACKSIDE ELECTRICAL CONTACTS TO BURIED POWER RAILS 有权
公开(公告)号：US20230093101A1
公开(公告)日：2023-03-23
申请号：US17481706
申请日：2021-09-22
申请人： International Business Machines Corporation
发明人： Ruilong XIE , Brent ANDERSON , Albert M. YOUNG , Kangguo CHENG , Julien FROUGIER , Balasubramanian PRANATHARTHIHARAN , Roy R. YU , Takeshi NOGAMI
IPC分类号： H01L29/40 , H01L29/165 , H01L29/423 , H01L29/417 , H01L29/06 , H01L29/66 , H01L29/786 , H01L27/12 , H01L23/528 , H01L23/522 , H01L21/762 , H01L21/84
摘要： A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

7. 发明申请

US20170012130A1 LARGE AREA CONTACTS FOR SMALL TRANSISTORS 审中-公开
标题翻译：小型晶体管的大面积接触
公开(公告)号：US20170012130A1
公开(公告)日：2017-01-12
申请号：US15273778
申请日：2016-09-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES, Inc. , STMICROELECTRONICS, INC.
发明人： Xiuyu CAI , Qing LIU , Ruilong XIE , Chun-Chen YEH
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L21/02 , H01L21/8234
摘要： A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.
摘要翻译：用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在垂直方向上至少包括基本上倾斜的部分。在一个实施例中，下层是FinFET的外延翅片。制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。

8. 发明申请

US20160190317A1 HETERO-CHANNEL FINFET 有权
公开(公告)号：US20160190317A1
公开(公告)日：2016-06-30
申请号：US14587655
申请日：2014-12-31
申请人： STMICROELECTRONICS, INC. , GLOBALFOUNDRIES INC. , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Qing LIU , Ruilong XIE , Chun-chen YEH , Xiuyu CAI
IPC分类号： H01L29/78 , H01L21/02 , H01L29/165 , H01L29/40 , H01L29/66 , H01L29/417
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/41783 , H01L29/6681 , H01L29/7842 , H01L29/7851
摘要： A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a fabrication process than is a FinFET device having a germanium channel. A FinFET device featuring the heterogeneous Si/SiGe channel includes a fin having a central region made of silicon and sidewall regions made of SiGe. A hetero-channel pFET device in particular has higher carrier mobility and less gate-induced drain leakage current than either a silicon device or a SiGe device. The hetero-channel FinFET permits the SiGe portion of the channel to have a Ge concentration in the range of about 25-40% and permits the fin height to exceed 40 nm while remaining stable.
摘要翻译：异构沟道FinFET器件在具有硅沟道的FinFET器件上提供增强的开关性能，并且比具有锗通道的FinFET器件更容易集成到制造工艺中。具有异质Si / SiGe沟道的FinFET器件包括具有由硅构成的中心区域和由SiGe制成的侧壁区域的翅片。异质沟道pFET器件特别地具有比硅器件或SiGe器件更高的载流子迁移率和更小的栅极引起漏极漏电流。异质沟道FinFET允许沟道的SiGe部分的Ge浓度在约25-40％的范围内，并且允许翅片高度超过40nm，同时保持稳定。

9. 发明申请

US20160049402A1 SEMICONDUCTOR DEVICE HAVING FINS WITH IN-SITU DOPED, PUNCH-THROUGH STOPPER LAYER AND RELATED METHODS 审中-公开
标题翻译：具有现场拨号，穿孔停止层的FINS的半导体器件及相关方法
公开(公告)号：US20160049402A1
公开(公告)日：2016-02-18
申请号：US14461769
申请日：2014-08-18
申请人： STMICROELECTRONICS, INC. , INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc.
发明人： Qing LIU , Chun-chen YEH , Ruilong XIE , Xiuyu CAl
IPC分类号： H01L27/092 , H01L29/161 , H01L29/10 , H01L29/06 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/308 , H01L29/167 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/26513 , H01L21/823807 , H01L21/823821 , H01L21/823892 , H01L29/0653 , H01L29/1083 , H01L29/161 , H01L29/167
摘要： A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region.
摘要翻译：制造半导体器件的方法可以包括形成彼此横向相邻的第一和第二半导体区域，并且每个半导体区域包括第一半导体材料。该方法还可以包括在包括第一半导体材料和第一掺杂剂的第二半导体区域上方形成原位掺杂的穿通阻挡层，并且在穿通阻挡层上方形成半导体缓冲层，通过阻挡层包括第一半导体材料。该方法还可以包括在半导体缓冲层之上形成第三半导体区域，其中第三半导体区域包括与第一半导体材料不同的第二半导体材料。此外，可以从第一半导体区域形成至少一个第一鳍片，并且可以从第二半导体区域，穿通阻挡层，半导体缓冲层和第三半导体区域形成至少一个第二鳍片。

10. 发明申请

US20140110794A1 FACILITATING GATE HEIGHT UNIFORMITY AND INTER-LAYER DIELECTRIC PROTECTION 有权
标题翻译：提高门高度均匀性和层间电介质保护
公开(公告)号：US20140110794A1
公开(公告)日：2014-04-24
申请号：US13654717
申请日：2012-10-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES, INC.
发明人： Ruilong XIE , Xiuyu CAI , Pranatharthiharan BALASUBRAMANIAN , Shom PONOTH
IPC分类号： H01L21/283 , H01L29/423
CPC分类号： H01L29/66545 , H01L21/31053 , H01L21/76819 , H01L21/76837 , H01L21/76897 , H01L29/6653
摘要： Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.
摘要翻译：提供了便于更换栅极处理的方法和由该方法形成的半导体器件。所述方法包括例如提供具有侧壁间隔物的多个牺牲栅电极，具有侧壁间隔物的牺牲栅电极至少部分地由第一介电材料隔开，其中第一介电材料凹入下牺牲栅电极和牺牲栅电极的上表面暴露并共面; 在牺牲栅电极，侧壁间隔物和第一介电材料上保形地沉积保护膜; 在所述保护膜上提供第二电介质材料，并且平坦化所述第二电介质材料，停止所述保护膜并在所述牺牲栅电极上暴露所述保护膜; 并且在牺牲栅电极之上打开保护膜以便于执行替换浇口工艺。

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