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1. 发明申请

US20220012741A1 FRAUD DETECTION USING MULTI-TASK LEARNING AND/OR DEEP LEARNING 有权
公开(公告)号：US20220012741A1
公开(公告)日：2022-01-13
申请号：US16923295
申请日：2020-07-08
申请人： International Business Machines Corporation
发明人： Jeetu Raj , Erik Richter Altman , Shyam Ramji , Ravi Nair
IPC分类号： G06Q20/40 , G06N20/00
摘要： Application of multi-task learning technique(s) to machine logic (for example, software) used to detect financial transactions that are fraudulent or at least considered likely to be fraudulent. Some embodiments include adjustments and/or additions to conventional multi-task learning techniques in order to make the multi-task learning techniques more suitable for use in fraud detection software. One example of this is compensation for class imbalances that are to be expected as between the likely-fraud and not-likely-fraud classes of data sets (for example, training data sets, runtime data sets).

2. 发明授权

US10762271B2 Model-based refinement of the placement process in integrated circuit generation 有权
公开(公告)号：US10762271B2
公开(公告)日：2020-09-01
申请号：US16145993
申请日：2018-09-28
申请人： International Business Machines Corporation
发明人： Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Benjamin N. Trombley , Paul G. Villarrubia
IPC分类号： G06F30/00 , G06F30/398 , G06F30/392 , G06F30/394
摘要： A system and method of performing model-based refinement of a placement of components in integrated circuit generation select one of the components as a candidate component and postulate a move of the candidate component from an original position to a new position. The method includes defining nets associated with the candidate component. An initial perimeter and a new perimeter associated with each of the one or more nets are defined. The initial perimeter includes the candidate component at its original position and the new perimeter includes the candidate component at its new position. The method includes quantifying a change from the initial perimeter and the new perimeter and the original position and the new position, and obtaining a model of wires interconnecting the candidate component to the components of each of the nets. A result of the placement is provided for manufacture of the integrated circuit.

3. 发明申请

US20200159882A1 PROPAGATING CONSTANTS OF STRUCTURED SOFT BLOCKS WHILE PRESERVING THE RELATIVE PLACEMENT STRUCTURE 审中-公开
公开(公告)号：US20200159882A1
公开(公告)日：2020-05-21
申请号：US16194381
申请日：2018-11-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Salim Shah , Rokesh Jayasundar , Shyam Ramji , Paul G. Villarrubia
IPC分类号： G06F17/50
摘要： A design system accesses at least one placement template for at least one structured soft block composed of a pre-defined set of cells with relative placement information for the pre-defined set of cells. The design system optimizes implementation of the at least one structured soft block by propagating constants while preserving relative placement structure of the pre-defined set of cells within each at least one structured soft block according to the respective at least one placement template accessed for the at least one structured soft block.

4. 发明授权

US10558775B2 Memory element graph-based placement in integrated circuit design 有权
公开(公告)号：US10558775B2
公开(公告)日：2020-02-11
申请号：US15848556
申请日：2017-12-20
申请人： International Business Machines Corporation
发明人： Myung-Chul Kim , Arjen Alexander Mets , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Alexander J. Suess , Benjamin Trombley , Paul G. Villarrubia
IPC分类号： G06F17/50
摘要： A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

5. 发明授权

US10140409B2 Large cluster persistence during placement optimization of integrated circuit designs 有权
公开(公告)号：US10140409B2
公开(公告)日：2018-11-27
申请号：US15234685
申请日：2016-08-11
申请人： International Business Machines Corporation
发明人： Myung-Chul Kim , Shyam Ramji , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
摘要： The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.

6. 发明申请

US20180121575A1 CRITICAL PATH STRAIGHTENING SYSTEM BASED ON FREE-SPACE AWARE AND TIMING DRIVEN INCREMENTAL PLACEMENT 审中-公开
公开(公告)号：US20180121575A1
公开(公告)日：2018-05-03
申请号：US15341814
申请日：2016-11-02
申请人： International Business Machines Corporation
发明人： Jinwook Jung , Frank Musante , Gi-Joon Nam , Shyam Ramji , Lakshmi Reddy , Gustavo Tellez , Cindy S. Washburn
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5072 , G06F2217/06 , G06F2217/84
摘要： A physical synthesis system includes a path straightening module, an ideal critical point identification (ID) module, and a free-space ID module. The path straightening module identifies at least one meandering critical path of a circuit, and generates a reference curve based on dimensions of the critical path. The ideal critical point ID module identifies at least one critical point on the reference curve. The free-space ID module identifies at least one free-space to receive a gate with respect to at least one critical point. The physical synthesis system further includes a free-space selector module and a gate modification module. The free-space selector module determines a modified slack timing value based on relocating the gate to the at least one free-space. The gate modification module moves the gate to the at least one free-space when the modified slack timing value is greater than an initial slack timing value.

7. 发明申请

US20180004885A1 HIERARCHICALLY AWARE INTERIOR PINNING FOR LARGE SYNTHESIS BLOCKS 有权
公开(公告)号：US20180004885A1
公开(公告)日：2018-01-04
申请号：US15198954
申请日：2016-06-30
申请人： International Business Machines Corporation
发明人： Matthew D. Affeldt , Christopher J. Berry , Randall J. Darden , Shyam Ramji , Eddy St. Juste
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.

8. 发明授权

US09697322B2 Hierarchical wire-pin co-optimization 有权
公开(公告)号：US09697322B2
公开(公告)日：2017-07-04
申请号：US14794871
申请日：2015-07-09
申请人： International Business Machines Corporation
发明人： Christopher J. Berry , Ajith Kumar M. Chandrasekaran , Randall J. Darden , Shyam Ramji , Sourav Saha
IPC分类号： G06F17/00 , G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F17/5077 , G06F2217/84
摘要： A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, performing macro-level physical synthesis at each of the plurality of macros, and providing feedback to the unit level controller based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks. The method also includes performing hierarchical co-optimization at the unit level controller based on the feedback from each of the plurality of macros to determine locations for the movable pins.

9. 发明申请

US20170132349A1 CONSTRAINT-DRIVEN PIN OPTIMIZATION FOR HIERARCHICAL DESIGN CONVERGENCE 有权
公开(公告)号：US20170132349A1
公开(公告)日：2017-05-11
申请号：US14936920
申请日：2015-11-10
申请人： International Business Machines Corporation
发明人： Christopher J. Berry , Randall J. Darden , Adam R. Jatkowski , Joseph J. Palumbo , Shyam Ramji , Sourav Saha , Timothy A. Schell , Eddy St. Juste
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5031 , G06F17/505 , G06F17/5081 , G06F2217/06
摘要： A computer-implemented method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, a system, and a computer program product are described. Aspects include providing an indication of candidate pins among a plurality of pins of a plurality of macros that may be moved, and providing constraints on a range of movement of one or more of the plurality of pins. Aspects also include performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints to generate pin locations and timing results.

10. 发明授权

US09519744B1 Merging of storage elements on multi-cycle signal distribution trees into multi-bit cells 有权
标题翻译：将多周期信号分配树上的存储元素合并成多位单元
公开(公告)号：US09519744B1
公开(公告)日：2016-12-13
申请号：US14960812
申请日：2015-12-07
申请人： International Business Machines Corporation
发明人： William R. Migatz , Shyam Ramji
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method, system, and computer program product to merge storage elements on multi-cycle signal distribution trees into multi-bit cells of an integrated circuit include determining initial placement regions and initial placement locations for a plurality of storage elements arranged in two or more levels on the one or more trees, determining potential merge storage elements among the plurality of storage elements, and merging one or more pairs of the potential merge storage elements across the one or more trees into the multi-bit cells based on satisfying an additional condition. The two or more levels of each of the one or more trees includes a root level closest to a tree source of the respective one or more trees and a leaf level closest to a tree sink of the respective one or more trees.
摘要翻译：将多周期信号分配树上的存储元件合并成集成电路的多位单元的方法，系统和计算机程序产品包括为布置在两个或多个层级中的多个存储元件确定初始放置区域和初始放置位置在所述一个或多个树上确定所述多个存储元件之间的潜在合并存储元件，并且基于满足附加条件将所述一个或多个树中的一对或多对所述潜在合并存储元件合并到所述多位单元中。一个或多个树中的每一个的两个或更多个级别包括最接近相应的一个或多个树的树源的根级别和最接近相应一个或多个树的树槽的叶级。

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