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1. 发明申请

US20160248577A1 FABRIC MULTIPATHING BASED ON DYNAMIC LATENCY-BASED CALCULATIONS 有权
标题翻译：基于动态延迟计算的织物多路径
公开(公告)号：US20160248577A1
公开(公告)日：2016-08-25
申请号：US15141612
申请日：2016-04-28
申请人： International Business Machines Corporation
发明人： Talha J. Ilyas , Keshav G. Kamble , Vijoy A. Pandey
IPC分类号： H04L7/02 , H04L12/26 , H04L7/00
CPC分类号： H04L7/02 , G06F1/12 , H04J3/0667 , H04L7/0054 , H04L41/0853 , H04L43/0852 , H04L45/121 , H04L45/20 , H04L45/245
摘要： In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to determine a lowest latency LAG port for each LAG in any path of a plurality of paths connecting a first device with a second device, and discover a configuration of a network fabric connecting the first device to the second device after determining the lowest latency LAG port for each LAG therein. The network fabric includes a plurality of devices interconnected with LAGs. Moreover, the embodied program instructions are executable by the processor to perform clock synchronization for each path of the plurality of paths and determine a latency for each path of the plurality of paths based on the clock synchronization and the lowest latency LAG port for each LAG included in the plurality of paths.
摘要翻译：在一个实施例中，计算机程序产品包括具有实施的程序指令的计算机可读存储介质，所述程序指令可由处理器执行，以使处理器确定多条路径中的任何路径中的每个LAG的最低等待时间LAG端口将第一设备与第二设备连接，并且在确定其中的每个LAG的最低等待时间LAG端口之后，发现将第一设备连接到第二设备的网络结构的配置。网络结构包括与LAG互连的多个设备。此外，所体现的程序指令可由处理器执行以对多个路径中的每个路径执行时钟同步，并且基于包括的每个LAG的时钟同步和最小等待时间LAG端口来确定多个路径中的每个路径的等待时间在多个路径中。

2. 发明申请

US20140304543A1 FABRIC MULTIPATHING BASED ON DYNAMIC LATENCY-BASED CALCULATIONS 有权
标题翻译：基于动态延迟计算的织物多路径
公开(公告)号：US20140304543A1
公开(公告)日：2014-10-09
申请号：US13859651
申请日：2013-04-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Talha J. Ilyas , Keshav G. Kamble , Vijoy A. Pandey
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/1601 , G06F1/1603 , H04J3/0667 , H04L45/121 , H04L45/20 , H04L45/245
摘要： In one embodiment, a system for determining latency in paths includes logic integrated with and/or executable by a processor, the logic being adapted to synchronize clocks of two devices connected via two or more link aggregation (LAG) ports and/or multiple devices within paths through a network fabric, determine a transit delay for each LAG port and/or path, store the transit delay for each LAG port to a LAG structure along with an identifier for the LAG port and/or for each path to an equal cost multi-path (ECMP) structure along with an identifier of the path, sort the LAG ports according to each LAG port's transit delay and mark a LAG port having the lowest latency, and sort the paths according to each path's transit delay and mark a path having the lowest latency, wherein each path has an equal path cost factor.
摘要翻译：在一个实施例中，用于确定路径中的等待时间的系统包括与处理器集成和/或可执行的逻辑，所述逻辑适于同步经由两个或多个链路聚合（LAG）端口和/或多个设备连接的两个设备的时钟通过网络结构的路径，确定每个LAG端口和/或路径的传输延迟，将每个LAG端口的传输延迟存储到LAG结构以及用于LAG端口的标识符和/或针对每个路径到相等成本多 -path（ECMP）结构以及路径的标识符，根据每个LAG端口的传输延迟对LAG端口进行排序，并标记具有最低延迟的LAG端口，并根据每个路径的传输延迟对路径进行排序，并标记具有最低延迟，其中每个路径具有相等的路径成本因子。

3. 发明授权

US09893874B2 Fabric multipathing based on dynamic latency-based calculations 有权
公开(公告)号：US09893874B2
公开(公告)日：2018-02-13
申请号：US15141612
申请日：2016-04-28
申请人： International Business Machines Corporation
发明人： Talha J. Ilyas , Keshav G. Kamble , Vijoy A. Pandey
IPC分类号： H04L7/00 , H04L7/02 , H04L12/26 , H04L12/24
CPC分类号： H04L7/02 , G06F1/12 , H04J3/0667 , H04L7/0054 , H04L41/0853 , H04L43/0852 , H04L45/121 , H04L45/20 , H04L45/245
摘要： In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to determine a lowest latency LAG port for each LAG in any path of a plurality of paths connecting a first device with a second device, and discover a configuration of a network fabric connecting the first device to the second device after determining the lowest latency LAG port for each LAG therein. The network fabric includes a plurality of devices interconnected with LAGs. Moreover, the embodied program instructions are executable by the processor to perform clock synchronization for each path of the plurality of paths and determine a latency for each path of the plurality of paths based on the clock synchronization and the lowest latency LAG port for each LAG included in the plurality of paths.

4. 发明授权

US09360885B2 Fabric multipathing based on dynamic latency-based calculations 有权
标题翻译：基于动态基于延迟的计算的结构多路径
公开(公告)号：US09360885B2
公开(公告)日：2016-06-07
申请号：US13859651
申请日：2013-04-09
申请人： International Business Machines Corporation
发明人： Talha J. Ilyas , Keshav G. Kamble , Vijoy A. Pandey
IPC分类号： G06F1/00 , G06F1/12 , G06F1/16
CPC分类号： G06F1/12 , G06F1/1601 , G06F1/1603 , H04J3/0667 , H04L45/121 , H04L45/20 , H04L45/245
摘要： In one embodiment, a system for determining latency in paths includes logic integrated with and/or executable by a processor, the logic being adapted to synchronize clocks of two devices connected via two or more link aggregation (LAG) ports and/or multiple devices within paths through a network fabric, determine a transit delay for each LAG port and/or path, store the transit delay for each LAG port to a LAG structure along with an identifier for the LAG port and/or for each path to an equal cost multi-path (ECMP) structure along with an identifier of the path, sort the LAG ports according to each LAG port's transit delay and mark a LAG port having the lowest latency, and sort the paths according to each path's transit delay and mark a path having the lowest latency, wherein each path has an equal path cost factor.
摘要翻译：在一个实施例中，用于确定路径中的等待时间的系统包括与处理器集成和/或可执行的逻辑，所述逻辑适于同步经由两个或多个链路聚合（LAG）端口和/或多个设备连接的两个设备的时钟通过网络结构的路径，确定每个LAG端口和/或路径的传输延迟，将每个LAG端口的传输延迟存储到LAG结构以及用于LAG端口的标识符和/或针对每个路径到相等成本多 -path（ECMP）结构以及路径的标识符，根据每个LAG端口的传输延迟对LAG端口进行排序，并标记具有最低延迟的LAG端口，并根据每个路径的传输延迟对路径进行排序，并标记具有最低延迟，其中每个路径具有相等的路径成本因子。

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