专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190114035A1 System-Wide Topology and Performance Monitoring GUI Tool with Per-Partition Views 审中-公开
公开(公告)号：US20190114035A1
公开(公告)日：2019-04-18
申请号：US16208044
申请日：2018-12-03
申请人： International Business Machines Corporation
发明人： William A. Bostic , Randall R. Heisch , Venkat R. Indukuru , Allan E. Johnson , Jesse L. Sathre , Philip L. Vitale
IPC分类号： G06F3/0481 , G06F11/30 , G06F11/32 , G06F3/0484 , G06F11/34
摘要： Mechanisms are provided for a graphical user interface tool for system-wide topology and performance monitoring with per-partition views. A graphical user interface application presents a consolidated view of physical and logical information based on the received performance data. The mechanisms provide real-time performance and utilization information in a visual format relative to the physical components in a topographical layout. The user may drill down to lower levels to view more detailed performance and utilization information.

2. 发明授权

US09600392B2 Tracking pipelined activity during off-core memory accesses to evaluate the impact of processor core frequency changes 有权
公开(公告)号：US09600392B2
公开(公告)日：2017-03-21
申请号：US14456198
申请日：2014-08-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Heather L. Hanson , Venkat R. Indukuru , Francis P. O'Connell , Karthick Rajamani
IPC分类号： G06F11/34 , G06F1/32
CPC分类号： G06F11/3466 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F3/0616 , G06F3/0653 , G06F3/0673 , G06F11/3024 , G06F11/3423 , Y02D10/126 , Y02D10/152
摘要： A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.

3. 发明申请

US20160364332A1 DYNAMIC DETECTION AND SOFTWARE CORRECTION OF INCORRECT LOCK AND ATOMIC UPDATE HINT BITS 审中-公开
标题翻译：不正确锁定和原子更新提示位置的动态检测和软件校正
公开(公告)号：US20160364332A1
公开(公告)日：2016-12-15
申请号：US14735429
申请日：2015-06-10
申请人： International Business Machines Corporation
发明人： Benjamin Carter Nowak , Guy Lynn Guthrie , Venkat R. Indukuru
IPC分类号： G06F12/08
CPC分类号： G06F9/00 , G06F11/00 , G06F11/073 , G06F11/0793
摘要： A hint bit detection and correction method uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.
摘要翻译：提示位检测和校正方法使用两个附加位作为每个缓存目录的一部分。这些位表示lwarx和stwcx指令（larx disp，stcx disp）。当出现提示位事件时，根据这两个位的组合，可能会显示一个提示位错误。一旦检测到提示位错误，就会发出软件中断，提示位校正方法识别和纠正不正确的提示位。

4. 发明授权

US09514046B1 Dynamic detection and software correction of incorrect lock and atomic update hint bits 有权
标题翻译：不正确的锁定和原子更新提示位的动态检测和软件校正
公开(公告)号：US09514046B1
公开(公告)日：2016-12-06
申请号：US14735429
申请日：2015-06-10
申请人： International Business Machines Corporation
发明人： Benjamin Carter Nowak , Guy Lynn Guthrie , Venkat R. Indukuru
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F9/00 , G06F11/00 , G06F11/073 , G06F11/0793
摘要： A hint bit detection and correction method uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.
摘要翻译：提示位检测和校正方法使用两个附加位作为每个缓存目录的一部分。这些位表示lwarx和stwcx指令（larx disp，stcx disp）。当出现提示位事件时，根据这两个位的组合，可能会显示一个提示位错误。一旦检测到提示位错误，就会发出软件中断，提示位校正方法识别和纠正不正确的提示位。

5. 发明申请

US20140282616A1 BIDIRECTIONAL COUNTING OF DUAL OUTCOME EVENTS 有权
标题翻译：双向比较活动的双向计数
公开(公告)号：US20140282616A1
公开(公告)日：2014-09-18
申请号：US13833776
申请日：2013-03-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Giles Roger Frazier , Venkat R. Indukuru
IPC分类号： G06F9/54
CPC分类号： G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A dual outcome event monitoring unit comprises a plurality of inputs, and a first counter. Each input is associated with an event and the first counter is a bidirectional counter. The dual outcome event monitoring unit is configured to increment the first counter in response to receiving an indication of the occurrence of a first event of a plurality of events. The first event is designated as an increment event. The dual outcome event monitoring unit is also configured to decrement the first counter responsive to receiving an indication of the occurrence of a second event of a plurality of events. The second event is designated as a decrement event.
摘要翻译：双重结果事件监控单元包括多个输入和第一计数器。每个输入与事件相关联，第一个计数器是一个双向计数器。双重结果事件监控单元被配置为响应于接收到多个事件的第一事件的发生的指示而递增第一计数器。第一个事件被指定为一个增量事件。双重结果事件监控单元还被配置为响应于接收到多个事件的第二事件的发生的指示而递减第一计数器。第二个事件被指定为递减事件。

6. 发明申请

US20140108770A1 IDENTIFYING LOAD-HIT-STORE CONFLICTS 有权
标题翻译：识别负荷 - 存储冲突
公开(公告)号：US20140108770A1
公开(公告)日：2014-04-17
申请号：US14109996
申请日：2013-12-18
申请人： International Business Machines Corporation
发明人： Venkat R. Indukuru , Alexander E. Mericas , Satish K. Sadasivam , Madhavi G. Valluri
IPC分类号： G06F9/445
CPC分类号： G06F9/44552 , G06F9/3834
摘要： A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.
摘要翻译：计算设备识别导致加载命中 - 存储冲突的加载指令和存储指令对。处理器标记指示处理器从存储器加载第一数据集的第一加载指令。处理器将特定目的寄存器中的第一加载指令所在的地址存储在存储器中。处理器确定第一个加载指令与第一个存储指令的加载命中 - 存储冲突的位置。如果处理器确定第一加载指令具有与第一存储指令的加载命中存储冲突，则处理器将第一数据集所在的地址存储在第二专用寄存器中的存储器中，对存储的第一数据集进行标记通过第一存储指令，将第一存储指令所在的地址存储在第三专用寄存器中，并增加冲突计数器。

7. 发明授权

US10895947B2 System-wide topology and performance monitoring GUI tool with per-partition views 有权
公开(公告)号：US10895947B2
公开(公告)日：2021-01-19
申请号：US16208044
申请日：2018-12-03
申请人： International Business Machines Corporation
发明人： William A Bostic , Randall R. Heisch , Venkat R. Indukuru , Allan E. Johnson , Jesse L. Sathre , Philip L. Vitale
IPC分类号： G06F3/0481 , G06F11/32 , G06F3/0484 , G06F11/34 , G06F11/30
摘要： Mechanisms are provided for a graphical user interface tool for system-wide topology and performance monitoring with per-partition views. A graphical user interface application presents a consolidated view of physical and logical information based on the received performance data. The mechanisms provide real-time performance and utilization information in a visual format relative to the physical components in a topographical layout. The user may drill down to lower levels to view more detailed performance and utilization information.

8. 发明授权

US10146396B2 System-wide topology and performance monitoring GUI tool with per-partition views 有权
公开(公告)号：US10146396B2
公开(公告)日：2018-12-04
申请号：US15075325
申请日：2016-03-21
申请人： International Business Machines Corporation
发明人： William A. Bostic , Randall R. Heisch , Venkat R. Indukuru , Allan E. Johnson , Jesse L. Sathre , Philip L. Vitale
IPC分类号： G06F3/048 , G06F3/0481 , G06F3/0484 , G06F11/30 , G06F11/32 , G06F11/34
摘要： Mechanisms are provided for a graphical user interface tool for system-wide topology and performance monitoring with per-partition views. A graphical user interface application presents a consolidated view of physical and logical information based on the received performance data. The mechanisms provide real-time performance and utilization information in a visual format relative to the physical components in a topographical layout. The user may drill down to lower levels to view more detailed performance and utilization information.

9. 发明授权

US09652356B2 Tracking pipelined activity during off-core memory accesses to evaluate the impact of processor core frequency changes 有权
公开(公告)号：US09652356B2
公开(公告)日：2017-05-16
申请号：US14723989
申请日：2015-05-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Heather L. Hanson , Venkat R. Indukuru , Francis P. O'Connell , Karthick Rajamani
IPC分类号： G06F1/32 , G06F1/00 , G06F11/34
CPC分类号： G06F11/3466 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F3/0616 , G06F3/0653 , G06F3/0673 , G06F11/3024 , G06F11/3423 , Y02D10/126 , Y02D10/152
摘要： A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.

10. 发明授权

US09495170B2 Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall 有权
标题翻译：在流水线停止期间确定一组指令内每个停顿的指令的每个失速原因
公开(公告)号：US09495170B2
公开(公告)日：2016-11-15
申请号：US14102807
申请日：2013-12-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Venkat R. Indukuru , Brian R. Konigsburg , Alexander E. Mericas , Benjamin W. Stolt
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： During a pipeline stall in a processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from functional units of the processor, finish reports including completion reasons for separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the finish reports. Once the monitoring unit receives a complete indicator from the completion unit, indicating the completion of the next to complete instruction group, the monitoring unit stores each determined stall reason aligned with each next to finish indicator in memory.
摘要翻译：在处理器中的流水线停止期间，直到完成指令组的下一个完成，监视单元从处理器的完成单元接收到指示从多个指令中指出最早的未完成指令的完成的完成指示符的一个完整的指导组。监视单元从处理器的功能单元接收完成报告，包括单独指令的完成原因。从完成原因的选择中，从完成报告中的与下一个完成指示符对齐的完成报告的选择中，监视单元从最多的指令的多个失败原因中确定至少一个失败原因。一旦监视单元从完成单元接收到完整的指示符，指示完成下一个完成指令组，则监视单元将每个确定的停顿原因与每个下一个完成指示符对准在存储器中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式