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1. 发明授权

US08536904B2 Command buffer circuit of semiconductor apparatus 有权
标题翻译：半导体装置的指令缓冲电路
公开(公告)号：US08536904B2
公开(公告)日：2013-09-17
申请号：US13217433
申请日：2011-08-25
申请人： Jae Bum Ko
发明人： Jae Bum Ko
IPC分类号： H03B1/00
CPC分类号： G11C8/12 , G11C8/06
摘要： A command buffer circuit of a semiconductor apparatus includes a first buffer configured to receive a first command signal and generate a first command control signal, a second buffer configured to receive a second command signal and generate a second command control signal, a second block configured to select and output the first command control signal or the second command control signal in response to a rank control signal, and a control signal generation block configured to generate the rank control signal in response to a single rank signal and a chip select signal.
摘要翻译：半导体装置的指令缓冲电路包括配置为接收第一命令信号并产生第一命令控制信号的第一缓冲器，被配置为接收第二命令信号并产生第二命令控制信号的第二缓冲器，被配置为响应于等级控制信号选择并输出第一命令控制信号或第二命令控制信号，以及控制信号生成块，被配置为响应于单个秩信号和片选信号而产生等级控制信号。

2. 发明授权

US08687439B2 Semiconductor apparatus and memory system including the same 有权
标题翻译：包括其的半导体装置和存储系统
公开(公告)号：US08687439B2
公开(公告)日：2014-04-01
申请号：US13181956
申请日：2011-07-13
申请人： Jae Bum Ko , Jong Chern Lee
发明人： Jae Bum Ko , Jong Chern Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1063 , G11C5/14 , G11C7/1084 , G11C7/109 , G11C8/12
摘要： A semiconductor memory apparatus includes one or more semiconductor chips configured to have predetermined capacity and structure; and a signal level control unit configured to control levels of external signals, which are input to the one or more semiconductor chips, in order to realize various capacities and structures using the one or more semiconductor chips.
摘要翻译：一种半导体存储装置，其具备：具有规定容量和结构的一个以上的半导体芯片; 以及信号电平控制单元，被配置为控制输入到所述一个或多个半导体芯片的外部信号的电平，以便实现使用所述一个或多个半导体芯片的各种容量和结构。

3. 发明授权

US08279702B2 Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US08279702B2
公开(公告)日：2012-10-02
申请号：US12840966
申请日：2010-07-21
申请人： Jae Bum Ko , Sang Jin Byeon
发明人： Jae Bum Ko , Sang Jin Byeon
IPC分类号： G11C8/00
CPC分类号： H01L25/0657 , G11C8/12 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.
摘要翻译：一种半导体装置，包括单芯片指定码设置块，被配置为生成具有不同码值的多组独立芯片指定码，或者至少两组独立芯片指定码具有相应的代码值，响应于多个芯片熔丝信号; 控制块，被配置为响应于所述多个芯片熔丝信号和所述多组独立芯片指定代码中的最高有效位而产生多个使能控制信号; 以及单独的芯片激活块，其被配置为响应于所述多个使能控制信号，将所述多个独立芯片指定码组中排除最高有效位的各个芯片指定码与芯片选择地址进行比较，以及根据比较结果使能多个个别芯片激活信号中的一个。

4. 发明申请

US20120124408A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20120124408A1
公开(公告)日：2012-05-17
申请号：US13166094
申请日：2011-06-22
申请人： Sang Jin BYEON , Jae Bum Ko
发明人： Sang Jin BYEON , Jae Bum Ko
IPC分类号： G06F1/06 , H01L23/498
CPC分类号： G11C5/04 , G11C16/20 , G11C2029/4402 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2924/00014
摘要： A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.
摘要翻译：半导体装置可以包括：第一芯片ID生成单元，被配置为通过第一穿通硅通孔接收使能信号和通过第二通过硅通孔的时钟信号，并生成第一芯片ID信号和延迟使能信号; 第二芯片ID生成单元，被配置为通过来自第一芯片ID生成单元的第三通过硅通孔和时钟信号接收延迟使能信号，并生成第二芯片ID信号; 第一芯片选择信号生成单元，被配置为接收第一芯片ID信号和主ID信号，并生成第一芯片选择信号; 以及第二芯片选择信号生成单元，被配置为接收第二芯片ID信号和主ID信号，并生成第二芯片选择信号。

5. 发明授权

US09030224B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US09030224B2
公开(公告)日：2015-05-12
申请号：US13339121
申请日：2011-12-28
申请人： Jae Bum Ko , Sang Jin Byeon
发明人： Jae Bum Ko , Sang Jin Byeon
IPC分类号： G01R31/02 , G06F1/32 , G01R31/3185 , G11C5/14 , G11C29/02
CPC分类号： G06F1/32 , G01R31/318558 , G11C5/14 , G11C29/021
摘要： A semiconductor integrated circuit includes a plurality of dies, wherein each of the dies is configured to enable a power circuit provided therein according to a power control signal, in a state in which the die was determined to be a good die or a fail die.
摘要翻译：半导体集成电路包括多个管芯，其中，所述管芯中的每一个被配置为在所述管芯被确定为良好管芯或者失效管芯的状态下根据功率控制信号使能设置在其中的电源电路。

6. 发明授权

US08339894B2 Address delay circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的地址延迟电路
公开(公告)号：US08339894B2
公开(公告)日：2012-12-25
申请号：US12970792
申请日：2010-12-16
申请人： Jae Bum Ko , Jong Chern Lee
发明人： Jae Bum Ko , Jong Chern Lee
IPC分类号： G11C8/06
CPC分类号： G11C8/18 , G11C8/04
摘要： An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses.
摘要翻译：半导体存储装置的地址延迟电路包括：控制脉冲生成单元，被配置为在输入读取写入脉冲之后产生与时钟的预定倍数相对应的时间的控制脉冲; 以及延迟单元，被配置为当输入所述控制脉冲时输出内部地址，其中所述内部地址被输入为外部地址。

7. 发明授权

US08526250B2 Address delay circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的地址延迟电路
公开(公告)号：US08526250B2
公开(公告)日：2013-09-03
申请号：US13219632
申请日：2011-08-27
申请人： Jae Bum Ko
发明人： Jae Bum Ko
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/406 , G11C8/06 , G11C8/18
摘要： An address delay circuit of a semiconductor memory apparatus includes a first group control pulse generation unit configured to generate a first control pulse after input of a first group column address strobe pulse and passage of a time corresponding to a first set multiple of one cycle of a clock, a second group control pulse generation unit configured to generate a second control pulse after input of a second group column strobe address pulse and passage of a time corresponding to a second set multiple of the one cycle of the clock, a first address storage unit configured to receive and store a first group external address in response to the first control pulse, and output a first group internal address, and a second address storage unit configured to receive and store a second group external address in response to the second control pulse, and output a second group internal address.
摘要翻译：半导体存储装置的地址延迟电路包括：第一组控制脉冲生成单元，被配置为在输入第一组列地址选通脉冲之后产生第一控制脉冲，并且通过与第一组列地址选通脉冲的一个周期的第一设定倍数相对应的时间时钟，第二组控制脉冲生成单元，被配置为在输入第二组列选通地址脉冲之后产生第二控制脉冲，并且对应于时钟的一个周期的第二设定倍数的时间过去;第一地址存储单元被配置为响应于所述第一控制脉冲接收和存储第一组外部地址，并且输出第一组内部地址，以及第二地址存储单元，被配置为响应于所述第二控制脉冲接收和存储第二组外部地址，并输出第二组内部地址。

8. 发明授权

US08509012B2 Precharge signal generation circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储装置的预充电信号生成电路
公开(公告)号：US08509012B2
公开(公告)日：2013-08-13
申请号：US13171850
申请日：2011-06-29
申请人： Jae Bum Ko
发明人： Jae Bum Ko
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C7/12 , G11C7/22
摘要： A precharge signal generation circuit of a semiconductor memory apparatus may comprise a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command; and a read/write bank precharge address generation section configured to delay a bank column address strobe signal by a second delay time set in response to the precharge command delayed in the read/write precharge command generation section, and generate one of a read bank precharge address and a write bank precharge address.
摘要翻译：半导体存储装置的预充电信号生成电路可以包括：读/写预充电命令生成部，被配置为响应于控制信号将预充电命令延迟设定的第一延迟时间，以产生读预充电命令和写预充电命令; 以及读/写组预充电地址生成部，被配置为将存储体列地址选通信号延迟响应于在读/写预充电命令生成部中延迟的预充电命令而设定的第二延迟时间，并且生成读存储体预充电地址和写银行预付地址。

9. 发明授权

US08503256B2 Column command buffer and latency circuit including the same 有权
标题翻译：列命令缓冲器和延迟电路包括相同
公开(公告)号：US08503256B2
公开(公告)日：2013-08-06
申请号：US12841095
申请日：2010-07-21
申请人： Jae Bum Ko
发明人： Jae Bum Ko
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/109 , G11C11/4076 , G11C11/4093 , G11C2207/2272
摘要： A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate internal column commands.
摘要翻译：列命令缓冲器包括可变延迟部分，其被配置为基于时钟的频率确定延迟时间，并且在延迟延迟时间之后输出列命令; 以及缓冲部，被配置为接收所述可变延迟部的输出并生成内部列命令。

10. 发明授权

US08400210B2 Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US08400210B2
公开(公告)日：2013-03-19
申请号：US12840212
申请日：2010-07-20
申请人： Jae Bum Ko , Sang Jin Byeon
发明人： Jae Bum Ko , Sang Jin Byeon
IPC分类号： H03K19/003
CPC分类号： G11C8/12
摘要： A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.
摘要翻译：半导体装置包括单独的芯片指定代码设置块，其被配置为响应于多个芯片熔丝信号而生成具有不同代码值的多个独立芯片指定代码或其中至少两个具有相同代码值的单独芯片指定代码; 以及单个芯片激活块，其被配置为响应于所述多个芯片熔丝信号来比较所述多个独立芯片指定代码与芯片选择地址，并且基于所述比较的结果来启用多个单独芯片激活信号中的一个。

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