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1. 发明授权

US08044979B2 Active display device and mixing type pixel driving method in active display device 有权
标题翻译：主动显示装置和混合型像素驱动方法在主动显示装置中
公开(公告)号：US08044979B2
公开(公告)日：2011-10-25
申请号：US12034795
申请日：2008-02-21
申请人： Jae Gan Ko
发明人： Jae Gan Ko
IPC分类号： G09G5/10
CPC分类号： G09G3/2081 , G09G3/3225 , G09G2300/08 , G09G2330/021 , G09G2340/0435 , G09G2360/16
摘要： A mixing type pixel driving method in an active display device includes generating a digital data for a selected pixel, first driving the selected pixel to be illuminated with a first illumination intensity, and second driving the selected pixel to be illuminated with a second illumination intensity in a second illumination interval. A relative ratio of the second illumination intensity to the first illumination intensity is changed according to the value of the digital data. The number of the converted bits by DAC is reduced. Therefore, the less bit DAC is adaptable for the mixing type pixel driving method and the layout area and the consumption current can be decreased.
摘要翻译：有源显示装置中的混合型像素驱动方法包括：生成用于所选择的像素的数字数据，首先以第一照明强度驱动所选择的被照明像素，并且以第二照明强度驱动所选择的要被照明的像素第二个照明间隔。第二照明强度与第一照明强度的相对比率根据数字数据的值而改变。 DAC减少转换位数。因此，较少位DAC适用于混合型像素驱动方法，并且可以减小布局面积和消耗电流。

2. 发明授权

US08009784B2 Clock embedded differential data receiving system for ternary lines differential signaling 有权
标题翻译：用于三线差分信号的时钟嵌入式差分数据接收系统
公开(公告)号：US08009784B2
公开(公告)日：2011-08-30
申请号：US12022248
申请日：2008-01-30
申请人： Jae Gan Ko
发明人： Jae Gan Ko
IPC分类号： H04L7/02
CPC分类号： H04L7/0008 , H04L7/0037 , H04L7/0337 , H04L25/0272
摘要： A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.
摘要翻译：用于三线差分信号的时钟嵌入式差分数据接收系统。时钟嵌入式差分数据接收系统包括：监视部分，其监测第一，第二和第三传送信号的电压电平以产生时钟信号;第一预数据和第二预数据;数据产生部分，其检测第一预先数据和第二预数据，并且产生具有第一预数据和第二预数据的解码的输出数据组，以及定时控制器，用于延迟时钟的转变时间点信号具有产生采样控制信号的延迟相位。

3. 发明授权

US07521977B2 Voltage-controlled oscillator generating output signal finely tunable in wide frequency range and variable delay circuits included therein 有权
标题翻译：产生输出信号的压控振荡器可在宽频率范围内精细调节，其中包括可变延迟电路
公开(公告)号：US07521977B2
公开(公告)日：2009-04-21
申请号：US11776684
申请日：2007-07-12
申请人： Jae Gan Ko
发明人： Jae Gan Ko
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00221 , H03L7/0995
摘要： A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous stage is provided as a second differential input signal. Each variable delay circuit includes a loading circuit including first and second loading units, a first input circuit including first and second input transistors gated by the first differential input signal, a second input circuit including third and fourth input transistors gated by the second differential input signal, first and second current sources connected between a first common node and a second power source and in electrical parallel with each other, and third and fourth current sources connected between a second common node and the second power source and in electrical parallel with each other.
摘要翻译：压控振荡器包括多个可变延迟电路，其中相邻前一级的第一差分输出信号被提供为第一差分输入信号，并且第二前级的第二差分输出信号被提供为第二差分输入信号。每个可变延迟电路包括一个包括第一和第二加载单元的加载电路，包括由第一差分输入信号选通的第一和第二输入晶体管的第一输入电路，包括由第二差分输入信号选通的第三和第四输入晶体管的第二输入电路连接在第一公共节点和第二电源之间并且彼此电并联的第一和第二电流源，以及连接在第二公共节点和第二电源之间并彼此电并联的第三和第四电流源。

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