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1. 发明授权

US07663398B1 Circuit and method for high impedance input/output termination in shut off mode and for negative signal swing 有权
标题翻译：关闭模式下高阻抗输入/输出端接和负信号摆幅的电路和方法
公开(公告)号：US07663398B1
公开(公告)日：2010-02-16
申请号：US12273368
申请日：2008-11-18
申请人： Jaeseo Lee , Gin S. Yee , Ming-Ju E. Lee
发明人： Jaeseo Lee , Gin S. Yee , Ming-Ju E. Lee
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0278 , H03K19/0005 , H04L25/0292
摘要： A circuit including control logic; and configurable impedance logic, operatively coupled to the control logic, comprising a configurable transistor structure operative to selectively change from a high impedance mode where the configurable transistor structure is configurable as a plurality of series connected diodes having their cathodes coupled together, and a low impedance mode where the configurable transistor structure is configurable to include a plurality of cascoded transistors. The circuit may further include at least one control signal line from the control logic to the configurable impedance logic, where the control signal line is operative to provide a control signal for configuring the configurable impedance logic.
摘要翻译：包括控制逻辑的电路; 以及可操作地耦合到所述控制逻辑的可配置阻抗逻辑，包括可配置晶体管结构，其可操作以选择性地从高阻抗模式改变，其中所述可配置晶体管结构可配置为多个串联连接的二极管，其阴极耦合在一起，并且低阻抗模式，其中可配置晶体管结构可配置为包括多个级联晶体管。电路还可以包括从控制逻辑到可配置阻抗逻辑的至少一个控制信号线，其中控制信号线可操作以提供用于配置可配置阻抗逻辑的控制信号。

2. 发明授权

US07487378B2 Asymmetrical IO method and system 有权
标题翻译：非对称IO方法和系统
公开(公告)号：US07487378B2
公开(公告)日：2009-02-03
申请号：US11231078
申请日：2005-09-19
申请人： Stephen Morein , Joseph Macri , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Stephen Morein , Joseph Macri , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： H04L7/02 , H04L7/0025 , H04L7/0091
摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.
摘要翻译：描述了非对称IO方法和系统。在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。共享资源包括一个共享相位内插器。在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

3. 发明授权

US08661300B1 Error detection in high-speed asymmetric interfaces 有权
标题翻译：高速非对称接口中的错误检测
公开(公告)号：US08661300B1
公开(公告)日：2014-02-25
申请号：US13169977
申请日：2011-06-27
申请人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F11/00
CPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于接口上的事务。基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

4. 发明授权

US08289056B2 Phase detector circuit for automatically detecting 270 and 540 degree phase shifts 有权
标题翻译：用于自动检测270度和540度相移的相位检测器电路
公开(公告)号：US08289056B2
公开(公告)日：2012-10-16
申请号：US12327787
申请日：2008-12-03
申请人： Min Xu , Ming-Ju E. Lee
发明人： Min Xu , Ming-Ju E. Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03D13/004 , H03L7/089 , H03L7/0891
摘要： Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating a substantially 270 degree phase shifted clock signal and a substantially 540 degree phase shifted clock signal, a phase detector receiving the system clock signal and the substantially 270 degree phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the substantially 270 degree phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.
摘要翻译：实施例包括实现用于延迟锁定环路（DLL）电路的相位检测器，该电路可操作以检测两个时钟信号之间基本上270度和基本上540度的相位差。在一个实施例中，DLL电路包括延迟线，其接收系统时钟信号并产生基本上270度的相移时钟信号和基本上540度的相移时钟信号，相位检测器接收系统时钟信号和基本270度相位并且被配置为在检测到系统时钟信号和基本上270度的相移时钟信号之间基本上为270度的相移时产生相应的上下信号，耦合到相位检测器的电荷泵，并且被配置为接收上升和下拉信号并响应于此产生控制信号，以及调节器电路，用于从电荷泵接收控制信号，并产生到延迟链的电压控制信号以控制系统时钟信号的延迟。

5. 发明授权

US08564347B2 Phase detector circuit for automatically detecting 270 and 540 degree phase shifts 有权
标题翻译：用于自动检测270度和540度相移的相位检测器电路
公开(公告)号：US08564347B2
公开(公告)日：2013-10-22
申请号：US13607045
申请日：2012-09-07
申请人： Min Xu , Ming-Ju E. Lee
发明人： Min Xu , Ming-Ju E. Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03D13/004 , H03L7/089 , H03L7/0891
摘要： Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating phase shifted clock signals, a phase detector receiving the system clock signal and phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.
摘要翻译：实施例包括实现用于延迟锁定环路（DLL）电路的相位检测器，该电路可操作以检测两个时钟信号之间基本上270度和基本上540度的相位差。在一个实施例中，DLL电路包括接收系统时钟信号并产生相移时钟信号的延迟线，接收系统时钟信号和相移时钟信号的相位检测器，并且被配置为在检测到在系统时钟信号和相移时钟信号之间基本为270度的相移，耦合到相位检测器的电荷泵，并且被配置为接收上升和下拉信号并响应于此产生控制信号，以及调节器电路从电荷泵接收控制信号，并产生到延迟链的电压控制信号，以控制系统时钟信号的延迟。

6. 发明授权

US08892963B2 Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines 有权
标题翻译：使用专用接口线路的高速非对称接口中的错误检测
公开(公告)号：US08892963B2
公开(公告)日：2014-11-18
申请号：US11595619
申请日：2006-11-09
申请人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F11/00 , H04L1/00 , G06F11/10 , G06F11/08
CPC分类号： H04L1/0045 , G06F11/08 , G06F11/10 , H04L1/0061 , H04L2001/0094
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件通过接口的READ和WRITE操作同时从一个接口的一行接收第二个组件的签名。与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于特定的READ或WRITE命令。基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

7. 发明授权

US08301930B2 System and apparatus for transmitting phase information from a client to a host between read and write operations 有权
标题翻译：用于在读取和写入操作之间将相位信息从客户端发送到主机的系统和装置
公开(公告)号：US08301930B2
公开(公告)日：2012-10-30
申请号：US12356804
申请日：2009-01-21
申请人： Stephen Morein , Joseph Macri , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Stephen Morein , Joseph Macri , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： H04L7/02 , H04L7/0025 , H04L7/0091
摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.
摘要翻译：描述了非对称IO方法和系统。在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。共享资源包括一个共享相位内插器。在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

8. 发明授权

US07996731B2 Error detection in high-speed asymmetric interfaces 有权
标题翻译：高速非对称接口中的错误检测
公开(公告)号：US07996731B2
公开(公告)日：2011-08-09
申请号：US11592074
申请日：2006-11-01
申请人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F11/00
CPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于接口上的事务。基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

9. 发明授权

US07934109B2 Low power mode unipolar current/voltage mode interface 有权
标题翻译：低功耗模式单极性电流/电压模式接口
公开(公告)号：US07934109B2
公开(公告)日：2011-04-26
申请号：US11732783
申请日：2007-04-03
申请人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.
摘要翻译：描述用于存储器接口的功耗降低过程的实施例。电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

10. 发明授权

US07752476B2 Fast transition from low-speed mode to high-speed mode in high-speed interfaces 有权
标题翻译：在高速接口中从低速模式快速转换到高速模式
公开(公告)号：US07752476B2
公开(公告)日：2010-07-06
申请号：US11804413
申请日：2007-05-17
申请人： Joseph Macri , Steven Morein , Ming-Ju E. Lee , Lin Chen
发明人： Joseph Macri , Steven Morein , Ming-Ju E. Lee , Lin Chen
IPC分类号： G01R31/28
CPC分类号： G06F1/3275 , G06F1/3225 , G11C7/1045 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2227 , Y02D10/14
摘要： Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.
摘要翻译：描述了在模拟定时电路初始化和变得可用的时间段期间继续在低功率模式下工作的存储器件和存储器控制器的实施例。在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行模式。参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由从低速模式向高速模式的转变将大大降低。

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