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1. 发明授权

US09268542B1 Cache contention management on a multicore processor based on the degree of contention exceeding a threshold 有权
标题翻译：基于超过阈值的争用程度，在多核处理器上进行缓存争用管理
公开(公告)号：US09268542B1
公开(公告)日：2016-02-23
申请号：US13096821
申请日：2011-04-28
申请人： Jason Mars , Robert Hundt , Neil A. Vachharajani
发明人： Jason Mars , Robert Hundt , Neil A. Vachharajani
IPC分类号： G06F9/46 , G06F13/00 , G06F9/45 , G06F9/30 , G06F9/52 , G06F13/372 , G06F13/30
CPC分类号： G06F8/4442 , G06F9/30 , G06F9/46 , G06F9/5016 , G06F9/526 , G06F13/30 , G06F13/372 , G06F2209/504 , G06F2209/508 , Y02D10/22
摘要： A first indicator of a first number of cache misses to a cache memory of a multicore processor for a first application over a first time period is received. The first application executes on a first core of the processor and a second application simultaneously executes on a second core of the processor during the first time period. The first and second cores share the cache memory. A second indicator of a second number of cache misses to the cache memory for the first application over a second time period is received. During the second time period, the first application executes on the first core and the second application does not execute on the second core. A degree of contention among the first and second applications is determined based on the first and second indicators, and execution of the second application is adjusted based on the determined degree of contention.
摘要翻译：接收在第一时间段内针对第一应用的多核处理器的高速缓冲存储器的第一数量的高速缓存未命中的第一指示符。第一应用在处理器的第一核上执行，并且第二应用在第一时间段期间同时在处理器的第二核上执行。第一和第二核共享缓存。接收在第二时间段内针对第一应用的高速缓存存储器的第二数量的高速缓存未命中的第二指示符。在第二时间段期间，第一应用在第一核上执行，第二应用不在第二核上执行。基于第一和第二指示符确定第一和第二应用程序之间的争用程度，并且基于所确定的争用程度来调整第二应用的执行。

2. 发明授权

US09135082B1 Techniques and systems for data race detection 有权
标题翻译：用于数据竞争检测的技术和系统
公开(公告)号：US09135082B1
公开(公告)日：2015-09-15
申请号：US13112945
申请日：2011-05-20
申请人： Tianwei Sheng , Neil A. Vachharajani , Stephane Eranian , Robert Hundt
发明人： Tianwei Sheng , Neil A. Vachharajani , Stephane Eranian , Robert Hundt
IPC分类号： G06F9/44 , G06F9/52 , G06F11/36 , G06F9/45
CPC分类号： G06F9/524 , G06F8/458 , G06F11/28 , G06F11/36 , G06F11/3632
摘要： A race detection mechanism can include running threads of a multithreaded program on a processor, the program being configured to produce locksets each of which indicate a set of one or more locks that a thread holds at a point in time. The mechanism can cause a performance monitoring unit included in the processor to monitor memory accesses caused by the threads and to produce samples based on the memory accesses, the samples being indicative of an accessed memory location. The mechanism can detect an existence of a data race condition based on the samples and the locksets. Detecting can include identifying a protected access to a memory location by a first thread of the threads and identifying an unprotected access to the memory location by a second thread of the threads. The process selectively outputs an indication of the data race condition.
摘要翻译：竞争检测机制可以包括在处理器上运行多线程程序的线程，该程序被配置为产生锁定器，每个锁定器指示线程在某个时间点保持的一个或多个锁的集合。该机制可以使处理器中包括的性能监视单元监视由线程引起的存储器访问并且基于存储器访问产生样本，该样本表示访问的存储器位置。该机制可以基于样本和锁定点来检测数据竞争条件的存在。检测可以包括通过线程的第一线程识别对存储器位置的受保护的访问，并且由线程的第二线程识别对存储器位置的不受保护的访问。该过程选择性地输出数据竞争条件的指示。

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