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1. 发明授权

US08526248B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US08526248B2
公开(公告)日：2013-09-03
申请号：US13162745
申请日：2011-06-17
申请人： Jeong Tae Hwang , Kang Youl Lee
发明人： Jeong Tae Hwang , Kang Youl Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C29/006 , G11C29/06 , G11C29/46
摘要： A semiconductor memory apparatus may include a bonding pad; a control signal pad; and an operation mode signal generation unit configured to generate a plurality of operation mode signals in response to a bonding signal inputted through the bonding pad and a control signal inputted through the control signal pad.
摘要翻译：半导体存储装置可以包括接合焊盘; 一个控制信号垫; 以及操作模式信号生成单元，被配置为响应于通过所述接合焊盘输入的接合信号和通过所述控制信号焊盘输入的控制信号而生成多个操作模式信号。

2. 发明授权

US08680841B2 Reference voltage generation circuitary for semiconductor apparatus and method for checking a reference voltage 有权
标题翻译：用于半导体装置的参考电压产生电路和用于检查参考电压的方法
公开(公告)号：US08680841B2
公开(公告)日：2014-03-25
申请号：US12983090
申请日：2010-12-31
申请人： Jeong Hun Lee , Yong Mi Kim , Jeong Tae Hwang
发明人： Jeong Hun Lee , Yong Mi Kim , Jeong Tae Hwang
IPC分类号： G05F1/607 , G05F1/614
CPC分类号： G11C5/147 , G11C29/021
摘要： A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.
摘要翻译：一种半导体装置，包括：被配置为生成多个不同的比较电压的比较电压生成单元，被配置为从外部系统接收生成代码的基准电压生成单元，根据生成代码选择所述多个不同的比较电压中的一个并产生参考电压，参考电压确定单元被配置为从外部系统接收生成代码和预期参考电压，检查预期参考电压的电平是否在目标范围内，并将检查结果输出到外部系统。

3. 发明授权

US07668026B2 Data I/O line control circuit and semiconductor integrated circuit having the same 失效
标题翻译：数据I / O线路控制电路和具有相同的半导体集成电路
公开(公告)号：US07668026B2
公开(公告)日：2010-02-23
申请号：US11962046
申请日：2007-12-20
申请人： Ki Myung Kyung , Jeong Tae Hwang
发明人： Ki Myung Kyung , Jeong Tae Hwang
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4076 , G11C11/4097 , G11C2207/002
摘要： A data I/O line control circuit includes a control unit for outputting a control signal after a predetermined time from an activation of a column select signal, and a switching unit for selectively separating a pair of first sub-middle I/O lines, which is coupled to a pair of local I/O lines located at one side of the switching unit, from a pair of second sub-middle I/O lines, which is coupled to both the pair of the local I/O lines and a data bus sense amplifier located at the other side of the switching unit.
摘要翻译：数据I / O线路控制电路包括：控制单元，用于在从列选择信号的激活开始的预定时间之后输出控制信号;以及切换单元，用于选择性地分离一对第一副中间I / O线，耦合到耦合到两对本地I / O线的一对第二中间I / O线的一对本地I / O线，位于开关单元的一侧，并且数据位于开关单元另一侧的总线读出放大器。

4. 发明授权

US08040747B2 Circuit and method for controlling precharge in semiconductor memory apparatus 有权
标题翻译：用于控制半导体存储装置中的预充电的电路和方法
公开(公告)号：US08040747B2
公开(公告)日：2011-10-18
申请号：US12650536
申请日：2009-12-30
申请人： Jeong Tae Hwang
发明人： Jeong Tae Hwang
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C8/18
摘要： A circuit for controlling precharge in a semiconductor memory apparatus includes a read clock driver configured to drive an internal clock signal and generate a read burst clock signal; a read precharge control unit configured to generate a read auto precharge signal in response to the read burst clock signal, a burst end signal, and a read write mode signal; a write clock driver configured to drive the internal clock signal and generate a write burst clock signal in response to the read write mode signal and a data input off signal; a write precharge control unit configured to generate a write auto precharge signal in response to the write burst clock signal, the burst end signal, a write latency signal, and a write address combination signal; and a precharge signal generation unit configured to combine the read and write auto precharge signals and generate an auto precharge signal.
摘要翻译：一种用于在半导体存储装置中控制预充电的电路包括：读时钟驱动器，被配置为驱动内部时钟信号并产生读突发时钟信号; 读取预充电控制单元，被配置为响应于所读取的突发时钟信号，突发结束信号和读取写入模式信号而产生读取的自动预充电信号; 写时钟驱动器，被配置为驱动内部时钟信号并响应于读写模式信号和数据输入关信号产生写突发时钟信号; 写预充电控制单元，被配置为响应于写突发时钟信号，突发结束信号，写等待时间信号和写地址组合信号产生写自动预充电信号; 以及预充电信号生成单元，被配置为组合所述读取和写入自动预充电信号并产生自动预充电信号。

5. 发明申请

US20110235443A1 VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME 失效
标题翻译：使用电压稳定电路和半导体存储器件
公开(公告)号：US20110235443A1
公开(公告)日：2011-09-29
申请号：US13155901
申请日：2011-06-08
申请人： Jeong Hun Lee , Yong Mi Kim , Jeong Tae Hwang
发明人： Jeong Hun Lee , Yong Mi Kim , Jeong Tae Hwang
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/147 , G11C7/02 , G11C7/22 , G11C7/222
摘要： A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.
摘要翻译：半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线响应于检测信号。

6. 发明申请

US20100332925A1 SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF TESTING THE SAME 失效
标题翻译：半导体存储装置及其测试方法
公开(公告)号：US20100332925A1
公开(公告)日：2010-12-30
申请号：US12649743
申请日：2009-12-30
申请人： Jeong Hun Lee , Yong Mi Kim , Jeong Tae Hwang
发明人： Jeong Hun Lee , Yong Mi Kim , Jeong Tae Hwang
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/46
摘要： A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.
摘要翻译：根据实施例的半导体存储装置包括测试模式控制器，第一数据对准单元，解码器，测试执行单元和第二数据对准单元。测试模式控制器被配置为响应于测试模式设置信号和读取命令而产生测试使能信号。第一数据对准单元被配置为并行地对准串联输入的第一输入数据，产生第一对准数据，并将其发送到第一数据驱动器。解码器被配置为响应于测试使能信号对第一对准数据进行解码并产生解码信号。测试执行单元被配置为响应于解码信号执行预设测试模式。第二数据对准单元被配置为响应于测试使能信号并行输入串联的第二输入数据，产生第二对准数据并将其发送到第二数据驱动器。

7. 发明申请

US20080304340A1 DATA I/O LINE CONTROL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME 失效
标题翻译：数据I / O线控制电路和具有相同功能的半导体集成电路
公开(公告)号：US20080304340A1
公开(公告)日：2008-12-11
申请号：US11962046
申请日：2007-12-20
申请人： Ki Myung Kyung , Jeong Tae Hwang
发明人： Ki Myung Kyung , Jeong Tae Hwang
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C11/4097 , G11C2207/002
摘要： A data I/O line control circuit includes a control unit for outputting a control signal after a predetermined time from an activation of a column select signal, and a switching unit for selectively separating a pair of first sub-middle I/O lines, which is coupled to a pair of local I/O lines located at one side of the switching unit, from a pair of second sub-middle I/O lines, which is coupled to both the pair of the local I/O lines and a data bus sense amplifier located at the other side of the switching unit.
摘要翻译：数据I / O线路控制电路包括：控制单元，用于在从列选择信号的激活开始的预定时间之后输出控制信号;以及切换单元，用于选择性地分离一对第一副中间I / O线，耦合到耦合到两对本地I / O线的一对第二中间I / O线的一对本地I / O线，位于开关单元的一侧，并且数据位于开关单元另一侧的总线读出放大器。

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