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1. 发明授权

US11635956B2 Fully pipelined hardware operator logic circuit for converting human-readable decimal character sequence floating-point representations to IEEE 754-2008 binary floating-point format representations 有权
公开(公告)号：US11635956B2
公开(公告)日：2023-04-25
申请号：US17555408
申请日：2021-12-18
申请人： Jerry D. Harthcock
发明人： Jerry D. Harthcock
IPC分类号： G06F9/30 , G06F5/00 , G06F12/06 , G06F9/355 , G06F9/54 , H03M7/24 , G06F7/483
摘要： A fully pipelined convertToBinaryFromDecimalCharacter hardware operator logic circuit configured to convert one or more human-readable decimal character sequence floating-point representations to IEEE 754-2008 binary floating-point representations every clock cycle. The circuit converts decimal character sequence floating-point representations up to 28 decimal digits in length to IEEE 754 binary64, binary32, or binary16 floating-point format representations.

2. 发明申请

US20220113968A1 Fully pipelined binary conversion hardware operator logic circuit 有权
公开(公告)号：US20220113968A1
公开(公告)日：2022-04-14
申请号：US17555408
申请日：2021-12-18
申请人： Jerry D. Harthcock
发明人： Jerry D. Harthcock
IPC分类号： G06F9/30 , G06F12/06 , G06F9/355 , G06F9/54
摘要： A universal floating-point Instruction Set Architecture (ISA) implemented entirely in hardware. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 “H=20” in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls “gobs” of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware H=20 convertFromDecimalCharacter conversion operators.

3. 发明授权

US07073048B2 Cascaded microcomputer array and method 失效
公开(公告)号：US07073048B2
公开(公告)日：2006-07-04
申请号：US10144524
申请日：2002-05-13
申请人： Jerry D. Harthcock
发明人： Jerry D. Harthcock
IPC分类号： G06F15/16
CPC分类号： G06F15/8007 , G06F9/382 , G06F9/3828 , G06F9/3853 , G06F9/3869 , G06F9/3889
摘要： A microcomputer array and method having a hyper-scalable, real-time monitoring and debug architecture in which several microcomputers are cascaded together into a single, more powerful unit. A cascaded instruction pipeline and related control circuitry allow a plurality of subprocessors or “proto-processors” to be cascaded with the instruction pipeline of a head processor or “nucleus processor” thereby creating an array of processors. The proto-processors may operate independently performing peripheral functions until a cascaded instruction takes priority and causes one or more proto-processors to perform the cascaded instruction and send the results to the nucleus processor. The processors may be microcomputers or Digital Signal Processors (DSPs).

4. 发明申请

US20220156070A1 UNIVERSAL FLOATING-POINT INSTRUCTION SET ARCHITECTURE FOR COMPUTING DIRECTLY WITH DECIMAL CHARACTER SEQUENCES AND BINARY FORMATS IN ANY COMBINATION 有权
公开(公告)号：US20220156070A1
公开(公告)日：2022-05-19
申请号：US17591963
申请日：2022-02-03
申请人： Jerry D. Harthcock
发明人： Jerry D. Harthcock
IPC分类号： G06F9/30 , G06F12/06 , G06F9/355 , G06F9/54
摘要： A universal floating-point Instruction Set Architecture (ISA) compute engine implemented entirely in hardware. The ISA compute engine computes directly with human-readable decimal character sequence floating-point representation operands without first having to explicitly perform a conversion-to-binary-format process in software. A fully pipelined convertToBinaryFromDecimalCharacter hardware operator logic circuit converts one or more human-readable decimal character sequence floating-point representations to IEEE 754-2008 binary floating-point representations every clock cycle. Following computations by at least one hardware floating-point operator, a convertToDecimalCharacterFromBinary hardware conversion circuit converts the result back to a human-readable decimal character sequence floating-point representation.

5. 发明申请

US20210049011A1 UNIVERSAL FLOATING-POINT INSTRUCTION SET ARCHITECTURE FOR COMPUTING DIRECTLY WITH DECIMAL CHARACTER SEQUENCES AND BINARY FORMATS IN ANY COMBINATION 有权
公开(公告)号：US20210049011A1
公开(公告)日：2021-02-18
申请号：US16943077
申请日：2020-07-30
申请人： Jerry D. Harthcock
发明人： Jerry D. Harthcock
IPC分类号： G06F9/30 , G06F9/355 , G06F9/54 , G06F12/06
摘要： A universal floating-point Instruction Set Architecture (ISA) implemented entirely in hardware. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 “H=20” in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls “gobs” of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware H=20 convertFromDecimalCharacter conversion operators.

6. 发明授权

US11635957B2 Hardware-implemented universal floating-point instruction set architecture for computing directly with human-readable decimal character sequence floating-point representation operands 有权
公开(公告)号：US11635957B2
公开(公告)日：2023-04-25
申请号：US17591963
申请日：2022-02-03
申请人： Jerry D. Harthcock
发明人： Jerry D. Harthcock
IPC分类号： G06F9/30 , G06F7/483 , G06F12/06 , G06F9/355 , G06F9/54 , H03M7/24 , G06F5/00
摘要： A universal floating-point Instruction Set Architecture (ISA) compute engine implemented entirely in hardware. The ISA compute engine computes directly with human-readable decimal character sequence floating-point representation operands without first having to explicitly perform a conversion-to-binary-format process in software. A fully pipelined convertToBinaryFromDecimalCharacter hardware operator logic circuit converts one or more human-readable decimal character sequence floating-point representations to IEEE 754-2008 binary floating-point representations every clock cycle. Following computations by at least one hardware floating-point operator, a convertToDecimalCharacterFromBinary hardware conversion circuit converts the result back to a human-readable decimal character sequence floating-point representation.

7. 发明申请

US20220376193A1 COMPLEX NANOSTRUCTURE CONFIGURABLE AS A TRANSISTOR, MULTIPLEXER, OR INFORMATION UNFOLDER 有权
公开(公告)号：US20220376193A1
公开(公告)日：2022-11-24
申请号：US17350805
申请日：2021-06-17
申请人： Jerry D. Harthcock
发明人： Jerry D. Harthcock
IPC分类号： H01L51/05 , H01L51/00
摘要： A complex nanostructure, which includes a first nanostructure component having at least one aperture in a side thereof; at least one second nanostructure component having a first end and a second end, wherein the first end of each of the at least one second nanostructure is inserted through a corresponding one of the at least one aperture in the first nanostructure, thereby forming at least one junction. Embodiments of the complex nanostructure include a bifurcated nanostructure transistor constructed of linear carbon nanotubes, a multiplexer constructed of a circular carbon nanotube and multiple linear carbon nanotubes, and an information unfolder constructed of linear or a combination of linear and circular carbon nanotubes. The nanotubes may optionally be decorated with genetic material such as single-strand or double-strand human DNA segments and/or may be modified by e-beam or ozone gas to add defects into the nanotubes to alter electrical/functional characteristics.

8. 发明授权

US11275584B2 Universal floating-point instruction set architecture for computing directly with decimal character sequences and binary formats in any combination 有权
公开(公告)号：US11275584B2
公开(公告)日：2022-03-15
申请号：US16943077
申请日：2020-07-30
申请人： Jerry D. Harthcock
发明人： Jerry D. Harthcock
IPC分类号： G06F9/30 , G06F9/355 , G06F9/54 , G06F12/06 , G06F9/32 , G06F9/35 , G06F9/38 , G06F12/02
摘要： A universal floating-point Instruction Set Architecture (ISA) implemented entirely in hardware. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 “H=20” in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls “gobs” of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware H=20 convertFromDecimalCharacter conversion operators.

9. 发明授权

US5303495A Personal weapon system 失效
标题翻译：个人武器系统
公开(公告)号：US5303495A
公开(公告)日：1994-04-19
申请号：US987788
申请日：1992-12-09
申请人： Jerry D. Harthcock
发明人： Jerry D. Harthcock
IPC分类号： F41A9/62 , F41A17/06 , F41A19/62
CPC分类号： F41A9/62 , F41A17/06 , F41A19/62
摘要： A personal weapon system comprises a microprocessor-controlled and electronically fired "blow-forward" handgun with a firing parameter memory device, digital security lock and safety device, directional compass, electronic rounds counter, integral keyboard and liquid crystal display, laser designator capability, programmable piezo-resistive trigger, and high frequency A.C. ignitable primer. A microprocessor receives information from a real time clock, Hall-effect rounds counter, and an integral Hall-effect compass. The processor displays this information on the LCD display for the operator. When a round is fired, the microprocessor records time and date, number of rounds fired, and direction of firing for crime lab analysis. The trigger pressure required to fire the handgun is programmable by the operator, and a corresponding trigger detonation mark is displayed on the LCD display. Trigger pressure exerted by the operator is displayed on the LCD display as a bar graph which lengthens in proportion to trigger pressure applied. The weapon fires when the bar graph reaches the trigger detonation mark.
摘要翻译：个人武器系统包括一个微处理器控制和电子发射的“前吹”手枪，具有击发参数记忆装置，数字安全锁和安全装置，定向罗盘，电子圆计数器，一体式键盘和液晶显示器，激光指示器能力，可编程压阻触发器和高频交流可点燃引脚。微处理器从实时时钟接收信息，霍尔效应回合计数器和一个整体霍尔效应罗盘。处理器在操作员的LCD显示屏上显示此信息。当一轮发射时，微处理器记录时间和日期，发射次数和犯罪实验室分析的射击方向。触发手枪所需的触发器压力可由操作员进行编程，液晶显示屏上显示相应的触发爆震标记。操作员施加的触发压力作为条形图显示在LCD显示屏上，该条形图与施加的触发压力成比例。当条形图达到触发爆震标记时，武器会触发。

10. 发明授权

US5235268A Test and measurement system 失效
标题翻译：测试和测量系统
公开(公告)号：US5235268A
公开(公告)日：1993-08-10
申请号：US791454
申请日：1991-11-13
申请人： Jerry D. Harthcock
发明人： Jerry D. Harthcock
IPC分类号： G01R1/067
CPC分类号： G01R1/06788
摘要： A system for simultaneously probing an electrical test circuit while remotely controlling the test equipment used to measure the probing. The probing is performed by the use of an electrical test probe of the type utilized with oscilloscopes or the like. Incorporated within the probe are switches adapted to detecting both lateral and longitudinal pressures exerted by the probe user. The lateral pressure is applied to the lower portion of the probe and depending upon the direction of the pressure causes a cursor displayed on the test equipment to move. The user moves the displayed cursor to the desired position, which position corresponds to a function or option of the test instrument. Upon selection, the user exerts a longitudinal force upon the probe, which force is detected by the probe and activates the selected function or option on the test instrument.
摘要翻译：同时探测电气测试电路的系统，同时远程控制用于测量探测的测试设备。探测通过使用与示波器等一起使用的类型的电测试探头进行。在探针中并入的开关适合于检测探头用户施加的横向和纵向压力。横向压力被施加到探头的下部，并且根据压力的方向导致测试设备上显示的光标移动。用户将显示的光标移动到所需位置，该位置对应于测试仪器的功能或选项。在选择时，用户在探头上施加纵向力，该力由探头检测并激活测试仪器上选定的功能或选项。

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