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    • 5. 发明申请
    • OPTICAL COMPONENT ASSEMBLY FOR USE WITH AN OPTICAL DEVICE
    • 光学元件组件与光学器件一起使用
    • US20140294345A1
    • 2014-10-02
    • US14306217
    • 2014-06-16
    • Victor Il'ich KoppJonathan SingerDaniel NeugroschlJongchul ParkMitchell S. Wlodawski
    • Victor Il'ich KoppJonathan SingerDaniel NeugroschlJongchul ParkMitchell S. Wlodawski
    • G02B6/28
    • G02B6/30
    • The inventive optical component assembly advantageously enables a multi-waveguide optical component (such as the inventive optical fiber coupler array, a multi-core optical fiber, etc.), to be coupled to at least one waveguide of an optical device at a predefined coupling angle. The optical component assembly of the present invention comprises a multi-waveguide optical component with an output end, a prism having an input surface, an output surface, and an internal reflective surface with a predefined reflection angle, and a GRIN lens, positioned between the component output end and the prism input surface, along a longitudinal axis of the multi-waveguide optical component. In accordance with the present invention, the length of the GRIN lens, and its refractive index gradient profile are optimized to form an optical image of the output end of the multi-waveguide optical component, at the output surface of the prism, thus enabling the output surface of the prism to be coupled to at least one waveguide of an optical device, with the predefined reflection angle corresponding to the angle at which the multi-waveguide optical component may be coupled to the optical device.
    • 本发明的光学部件组件有利地使得多波导光学部件(例如本发明的光纤耦合器阵列,多芯光纤等)能够以预定的耦合耦合到光学器件的至少一个波导 角度。 本发明的光学部件组件包括具有输出端的多波导光学部件,具有输入表面的棱镜,输出表面和具有预定反射角的内部反射表面,以及位于 分量输出端和棱镜输入表面沿着多波导光学部件的纵向轴线。 根据本发明,GRIN透镜的长度及其折射率梯度分布被优化以在棱镜的输出表面上形成多波导光学部件的输出端的光学图像,因此能够 所述棱镜的输出表面将被耦合到光学装置的至少一个波导,其中所述预定反射角度对应于所述多波导光学部件可耦合到所述光学装置的角度。
    • 6. 发明授权
    • Methods of manufacturing self aligned buried contact electrodes for vertical channel transistors
    • 制造用于垂直沟道晶体管的自对准埋入接触电极的方法
    • US08338254B2
    • 2012-12-25
    • US13270835
    • 2011-10-11
    • Jongchul ParkJinyoung KimSangsup Jeong
    • Jongchul ParkJinyoung KimSangsup Jeong
    • H01L21/336
    • H01L27/10876H01L21/823487
    • A semiconductor device including vertical field effect transistors may comprise a buried insulating film stacked on a semiconductor substrate and spaced apart first and second active regions vertically penetrating the buried insulating film. The active regions and the buried insulating film are covered with an interlayer insulating film. An upper interconnection is disposed in the interlayer insulating film. A gate electrode extends from a part of the upper interconnection into the buried insulating film between the first and second active regions. A protective film pattern is disposed to cover a top surface of the upper interconnection. First and second buried contact electrodes penetrating the interlayer insulating film to be in contact with top surfaces of the first and second active regions are provided. Related manufacturing methods are also described.
    • 包括垂直场效应晶体管的半导体器件可以包括堆叠在半导体衬底上的掩埋绝缘膜,并且垂直穿过埋入绝缘膜的间隔开的第一和第二有源区。 有源区和掩埋绝缘膜被层间绝缘膜覆盖。 上部互连布置在层间绝缘膜中。 栅电极从上互连的一部分延伸到第一和第二有源区之间的掩埋绝缘膜。 设置保护膜图案以覆盖上互连的顶表面。 提供穿透层间绝缘膜以与第一和第二有源区域的顶表面接触的第一和第二埋入接触电极。 还描述了相关的制造方法。
    • 8. 发明申请
    • METHOD FOR ETCHING METAL LAYER AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
    • 用于蚀刻金属层的方法和使用其制造半导体器件的方法
    • US20140024138A1
    • 2014-01-23
    • US13941071
    • 2013-07-12
    • Hyungjoon KwonKen TokashikiJongchul Park
    • Hyungjoon KwonKen TokashikiJongchul Park
    • H01L21/3065H01L43/12
    • H01L21/3065C23F4/00H01L21/32136H01L43/12
    • The inventive concepts disclosed herein include, for instance, methods for etching a metal layer and methods for manufacturing a semiconductor device using the etched metal layer. A wafer including a metal layer and a mask layer on the metal layer may be loaded into a process chamber. An etching gas may be supplied into the process chamber to etch the metal layer exposed by the mask layer. After the etching process, the mask layer may be removed. The etching gas can include phosphorus (P) and fluorine (F). An RF power may be constantly or selectively supplied to the process chamber, or different levels of RF power can be selectively supplied. An etching gas can be supplied to the process chamber when the RF power is off or at a lower level. A surface activation gas can be supplied when the RF power is on or at a higher level.
    • 本文公开的发明构思包括例如蚀刻金属层的方法和使用蚀刻金属层制造半导体器件的方法。 在金属层上包括金属层和掩模层的晶片可以被加载到处理室中。 可以将蚀刻气体供应到处理室中以蚀刻由掩模层暴露的金属层。 在蚀刻工艺之后,可以去除掩模层。 蚀刻气体可以包括磷(P)和氟(F)。 RF功率可以被恒定地或选择性地提供给处理室,或者可以选择性地提供不同级别的RF功率。 当RF功率关闭或处于较低水平时,可将蚀刻气体供应到处理室。 当RF功率开启或处于较高水平时,可以提供表面活化气体。