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1. 发明授权

US08082397B1 Private slot 有权
标题翻译：私人插槽
公开(公告)号：US08082397B1
公开(公告)日：2011-12-20
申请号：US10955136
申请日：2004-09-30
申请人： Josef Ezra , Adi Ofer
发明人： Josef Ezra , Adi Ofer
IPC分类号： G06F12/02
CPC分类号： G06F12/084
摘要： Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache. Each director may obtain a cache slot from a private stack of nondata cache slots in addition to accessing a shared cache used by all directors.
摘要翻译：描述了与缓存管理相关联使用的技术和标准。高速缓存可以被组织为多个存储体，其中每个存储体包括多个时隙。每个存储体具有包括标签区段组的相关控制槽。每个高速缓存槽具有包括指示相关高速缓存槽的可用性的位值的对应标签，以及指示使用槽中的数据的最后时间的时间戳。高速缓存可以由多个处理器共享。使用原子比较和交换指令实现高速缓存槽的独占访问。可以调整高速缓存中的时隙的时间戳以指示影响特定部分数据保留在高速缓存中的时间量的时隙的年龄。除了访问所有董事使用的共享缓存之外，每个董事可以从非数据缓存槽的私有堆栈获得高速缓存槽。

2. 发明授权

US07246187B1 Method and apparatus for controlling exclusive access to a shared resource in a data storage system 有权
标题翻译：用于控制对数据存储系统中的共享资源的独占访问的方法和装置
公开(公告)号：US07246187B1
公开(公告)日：2007-07-17
申请号：US10955033
申请日：2004-09-30
申请人： Josef Ezra , Adi Ofer
发明人： Josef Ezra , Adi Ofer
IPC分类号： G06F12/14
CPC分类号： G06F12/084 , G06F9/526
摘要： A method for controlling exclusive access to a resource shared by multiple processors in a data storage system includes providing a system lock procedure to permit a processor to obtain a lock on the shared resource preventing other processors from accessing the shared resource and providing a faked lock procedure to indicate to the system lock procedure that a processor has a lock on the shared resource where such a lock does not exist, and wherein the faked lock procedure prevents another processor from obtaining the lock on the shared resource, but does not prevent other processors from accessing the shared resource. A data storage system according to the invention includes a shared resource, a plurality of processors coupled to the shared resource through a communication channel, and a lock services procedure providing the system lock procedure and the faked lock procedure. In one embodiment, the shared resource is a cache and the system lock procedure permits a processor to lock the entire cache whereas the faked lock procedure is implemented by a processor seeking exclusive access of a cache slot.
摘要翻译：用于控制对数据存储系统中的多个处理器共享的资源的独占访问的方法包括提供系统锁定过程以允许处理器获得共享资源上的锁定，防止其他处理器访问共享资源并提供伪造的锁定过程为了向系统锁定过程指示处理器对不存在这样的锁的共享资源上的锁定，并且其中伪造的锁程序防止另一个处理器获得共享资源上的锁定，但是不阻止其他处理器访问共享资源。根据本发明的数据存储系统包括共享资源，通过通信信道耦合到共享资源的多个处理器，以及提供系统锁定过程和假锁定过程的锁定服务过程。在一个实施例中，共享资源是高速缓存，并且系统锁定过程允许处理器锁定整个高速缓存，而假的锁定过程由寻求高速缓存槽的独占访问的处理器来实现。

3. 发明授权

US06941492B1 Debugging tool for efficient switching between targets in a multi-processor environment 有权
标题翻译：用于在多处理器环境中有效切换目标的调试工具
公开(公告)号：US06941492B1
公开(公告)日：2005-09-06
申请号：US10068079
申请日：2002-02-05
申请人： Josef Ezra , Eli Shagam
发明人： Josef Ezra , Eli Shagam
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/362
摘要： A debugger mechanism to support multiple active targets and efficient switching between multiple active targets, in particular, heterogeneous targets, in a multiprocessing environment.
摘要翻译：一种调试器机制，用于在多处理环境中支持多个活动目标和多个活动目标（特别是异构目标）之间的有效切换。

4. 发明授权

US07177853B1 Cache management via statistically adjusted time stamp queue 有权
标题翻译：通过统计调整的时间戳队列缓存管理
公开(公告)号：US07177853B1
公开(公告)日：2007-02-13
申请号：US10080321
申请日：2002-02-21
申请人： Josef Ezra , Yechiel Yochai , Daniel Lambright , Sachin More , Yedidia Atzmony
发明人： Josef Ezra , Yechiel Yochai , Daniel Lambright , Sachin More , Yedidia Atzmony
IPC分类号： G06F17/30
CPC分类号： G06F12/0871 , G06F12/084 , G06F12/12 , Y10S707/99931
摘要： Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associate control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache.
摘要翻译：描述了与缓存管理相关联使用的技术和标准。高速缓存可以被组织为多个存储体，其中每个存储体包括多个时隙。每个存储体都有一个关联控制槽，包括一组标签区。每个高速缓存槽具有包括指示相关高速缓存槽的可用性的位值的对应标签，以及指示使用槽中的数据的最后时间的时间戳。高速缓存可以由多个处理器共享。使用原子比较和交换指令实现高速缓存槽的独占访问。可以调整高速缓存中的时隙的时间戳以指示影响特定部分数据保留在高速缓存中的时间量的时隙的年龄。

5. 发明授权

US07155573B1 Cache fall through time estimation 有权
标题翻译：缓存通过时间估计下降
公开(公告)号：US07155573B1
公开(公告)日：2006-12-26
申请号：US10853035
申请日：2004-05-25
申请人： Orit Levin-Michael , Josef Ezra
发明人： Orit Levin-Michael , Josef Ezra
IPC分类号： G06F12/08
CPC分类号： G06F12/123 , G06F11/3438 , G06F12/0866 , G06F2201/885
摘要： A method for estimating the fall through time of a cache includes maintaining local statistics associated with each data cache slot replaced by a processor, reading from a memory global statistics related to each data cache slot replaced by a plurality of processors, calculating new global statistics, and estimating a fall through time of the cache in response to the global statistics at a predetermined rate. When the global statistics are the result of at least a threshold number of data cache slots having been replaced, the new global statistics are calculated by weighting the global statistics by a factor of less than one and adding the weighted global statistics to the local statistics. When the global statistics are not the result of at least a threshold number of data cache slots having been replaced, the new global statistics are calculated by adding a time related to the lapsed time to a global sum value associated with the time stamp difference of the replaced data cache slots. In a multi-processor computer system, each of the processors accesses the global memory to update the global statistics at a different time. The fall through time is estimated continuously at a first predetermined rate and the global statistics are updated at a second predetermined rate that, in one embodiment, is a multiple of the first predetermined rate.
摘要翻译：用于估计高速缓存的下降时间的方法包括维护与由处理器取代的每个数据高速缓冲存储器相关联的本地统计信息，从与由多个处理器取代的每个数据高速缓冲存储器相关的存储器全局统计信息读取，计算新的全局统计信息，以及响应于预定速率的全局统计来估计缓存的下降时间。当全局统计信息是已被替换的至少一个阈值数量的高速缓存槽的结果时，通过将全局统计量加权小于1的因子来计算新的全局统计信息，并将加权的全局统计信息加到本地统计信息中。当全局统计信息不是至少已经被替换的数据高速缓冲存储器的阈值数量的结果时，通过将与经过的时间相关的时间相加到与时间戳差异相关联的全局和值来计算新的全局统计信息取代了数据缓存槽位。在多处理器计算机系统中，每个处理器访问全局存储器以在不同的时间更新全局统计信息。以第一预定速率连续地估计下降时间，并且以一个实施例中的第一预定速率的倍数以第二预定速率更新全局统计。

6. 发明授权

US07047366B1 QOS feature knobs 有权
标题翻译： QOS功能旋钮
公开(公告)号：US07047366B1
公开(公告)日：2006-05-16
申请号：US10463247
申请日：2003-06-17
申请人： Josef Ezra
发明人： Josef Ezra
IPC分类号： G06F12/00
CPC分类号： G06F12/0868 , G06F12/0804 , G06F2212/282
摘要： Described are various quality of service (QOS) parameters that may be used in characterizing device behavior in connection with a cache. A Partition parameter indicates which portions of available cache may used with data of an associated device. A Survival parameter indicates how long data of an associate device should remain in cache after use. A Linearity parameter indicates a likelihood factor that subsequent data tracks may be used such that this parameter may be used in determining whether to prefetch data. A Flush parameter indicates how long data should remain in cache after a write pending slot is returned to cache after being written out to the actual device. The QOS parameters may be included in configuration data. The QOS parameter values may be read and/or modified.
摘要翻译：描述了可用于表征与高速缓存相关联的设备行为的各种服务质量（QOS）参数。分区参数指示可用缓存的哪些部分可以与关联设备的数据一起使用。生存参数表示使用后关联设备的数据应保留在缓存中的时间长度。线性参数指示可以使用后续数据轨迹的似然因子，使得该参数可以用于确定是否预取数据。 “刷新”参数表示在将写入挂起的插槽写入实际设备后，缓存中的数据应保留多长时间。 QOS参数可能包含在配置数据中。可以读取和/或修改QOS参数值。

7. 发明授权

US07716642B1 Techniques for detecting coding incompatibilities 有权
标题翻译：检测编码不兼容性的技术
公开(公告)号：US07716642B1
公开(公告)日：2010-05-11
申请号：US11120602
申请日：2005-05-03
申请人： Ofer E. Michael , Josef Ezra , Dar S. Efroni
发明人： Ofer E. Michael , Josef Ezra , Dar S. Efroni
IPC分类号： G06F9/44
CPC分类号： G06F11/3624 , G06F11/3604
摘要： Described are techniques for detecting incompatibilities. A first contents of a data item is determined in accordance with a first set of conventions associated with a first processor architecture. A second contents of said data item is determined in accordance with a second set of conventions associated with a second processor architecture and including at least one convention that is not included in said first set. An actual difference between the first contents and the second contents is determined. It is determined whether the actual difference is expected. If the actual difference is not expected, the data item is flagged as an incompatibility candidate. Code referencing the data item is examined to determine any coding incompatibilities due to coding dependencies.
摘要翻译：描述了检测不兼容性的技术。根据与第一处理器架构相关联的第一组约定来确定数据项的第一内容。所述数据项的第二内容根据与第二处理器体系结构相关联的第二组约定来确定，并且包括不包括在所述第一组中的至少一个约定。确定第一内容和第二内容之间的实际差异。确定实际差异是否预期。如果实际的差异是不可预期的，数据项被标记为不兼容的候选者。检查引用数据项的代码，以确定由于编码依赖性而导致的任何编码不兼容性。

8. 发明授权

US07401322B1 Software debugging tool 有权
标题翻译：软件调试工具
公开(公告)号：US07401322B1
公开(公告)日：2008-07-15
申请号：US09962485
申请日：2001-09-25
申请人： Eli Shagam , Josef Ezra , Avihu Goral
发明人： Eli Shagam , Josef Ezra , Avihu Goral
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F11/3676
摘要： In a method for testing computer code, each branch that occurs within the machine-readable code is located. A first tracepoint is placed immediately after the beginning of the branch and a second tracepoint at the target address of each branch, each tracepoint generating an indicator. When the machine-readable code with the tracepoints is executed on the target computer, the method identifies those indicators that have been generated by their corresponding tracepoints, thereby permitting determination of those branches that the program control flow has not passed through. The test cases are modified to exercise the previously omitted branches, and the converted code is re-executed, until all branches have been properly exercised. The tracepoints are automatically eliminated after they have performed their intended function.
摘要翻译：在用于测试计算机代码的方法中，位于机器可读代码内的每个分支都位于该位置。在分支开始之后立即放置第一个跟踪点，并在每个分支的目标地址处放置第二个跟踪点，每个跟踪点生成一个指示符。当在目标计算机上执行具有跟踪点的机器可读代码时，该方法识别由其相应跟踪点生成的那些指示符，从而允许确定程序控制流未通过的那些分支。修改测试用例以执行先前省略的分支，并重新执行转换后的代码，直到所有分支都已正确运行。跟踪点在执行预定功能后自动消除。

9. 发明授权

US07216336B1 Sequential event monitoring module 有权
标题翻译：顺序事件监控模块
公开(公告)号：US07216336B1
公开(公告)日：2007-05-08
申请号：US10375991
申请日：2003-02-28
申请人： Josef Ezra , Ohad Zeliger
发明人： Josef Ezra , Ohad Zeliger
IPC分类号： G06F9/45
CPC分类号： G06F11/3624
摘要： A debugger mechanism that provides for debugging source code of a target by correlating messages in a log file associated with source code with corresponding lines of the source code.
摘要翻译：调试器机制，通过将与源代码相关联的日志文件中的消息与源代码的相应行相关联来提供对目标的源代码的调试。

10. 发明授权

US07143393B1 Method for cache management for positioning cache slot 有权
标题翻译：缓存管理定位缓存槽的方法
公开(公告)号：US07143393B1
公开(公告)日：2006-11-28
申请号：US10178085
申请日：2002-06-24
申请人： Josef Ezra , Daniel Lambright
发明人： Josef Ezra , Daniel Lambright
IPC分类号： G06F9/44 , G06F12/00
CPC分类号： G06F12/0871 , G06F12/084 , G06F12/12 , Y10S707/99931
摘要： Described are techniques used in connection with cache management. Data included in a cache slot is put “on parole” with a first cache hit while waiting for subsequent cache hits. If a subsequent hit is received to the cache slot, it remains in the cache for a longer time period than a slot having only a first cache hit. The cache may be organized as a plurality of memory banks of cache slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag, and a time stamp. The time stamp of slots in the cache may be adjusted affecting the amount of time a particular portion of data remains in the cache.
摘要翻译：描述了与高速缓存管理有关的技术。包含在缓存插槽中的数据在等待后续缓存命中时被放置在“假释”上，并带有第一个缓存命中。如果随后的命中被接收到高速缓存时隙，则其在高速缓存中保持比仅具有第一高速缓存命中的时隙更长的时间段。高速缓存可以被组织为高速缓存槽的多个存储器组。每个存储体具有包括标签区段组的相关控制槽。每个缓存槽具有相应的标签和时间戳。可以调整高速缓存中的时隙的时间戳影响数据的特定部分保留在高速缓存中的时间量。

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