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1. 发明授权

US07663234B2 Package of a semiconductor device with a flexible wiring substrate and method for the same 有权
标题翻译：具有柔性布线基板的半导体器件的封装及其方法
公开(公告)号：US07663234B2
公开(公告)日：2010-02-16
申请号：US11420453
申请日：2006-05-25
申请人： Joseph Sun , Kuang-Chih Cheng , Ming-Chieh Chen , Kevin Lee , Jui-Hsiang Pan
发明人： Joseph Sun , Kuang-Chih Cheng , Ming-Chieh Chen , Kevin Lee , Jui-Hsiang Pan
IPC分类号： H01L21/00 , H01L23/48
CPC分类号： H01L27/14618 , H01L23/49816 , H01L23/4985 , H01L27/14621 , H01L27/14627 , H01L27/14634 , H01L27/14683 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/13 , H01L2224/45144 , H01L2224/48091 , H01L2924/16235 , H05K3/323 , H05K3/361 , H05K2201/0367 , Y10T29/49144 , H01L2924/00014 , H01L2924/00
摘要： A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a flexible wiring substrate having at least one contact section being electrically connected with the bump by the adhesive layer. The present invention makes the flexible wiring substrate directly conductively attached onto the semiconductor substrate. The package size is shrunk and the cost down can be obtained.
摘要翻译：提供具有柔性布线基板的半导体器件的封装及其方法。该半导体器件的封装包括：半导体衬底，其表面上具有至少一个衬垫，与焊盘接合的凸块，凸块上的粘合剂层;以及柔性布线衬底，具有至少一个接触部分与由粘合剂层撞击。本发明使柔性布线基板直接导电地附着在半导体基板上。包装尺寸缩小，可以降低成本。

2. 发明授权

US07303400B2 Package of a semiconductor device with a flexible wiring substrate and method for the same 有权
标题翻译：具有柔性布线基板的半导体器件的封装及其方法
公开(公告)号：US07303400B2
公开(公告)日：2007-12-04
申请号：US11050814
申请日：2005-01-27
申请人： Joseph Sun , Kuang-Chih Cheng , Ming-Chieh Chen , Kevin Lee , Jui-Hsiang Pan
发明人： Joseph Sun , Kuang-Chih Cheng , Ming-Chieh Chen , Kevin Lee , Jui-Hsiang Pan
IPC分类号： H01R12/00
CPC分类号： H01L27/14618 , H01L23/49816 , H01L23/4985 , H01L27/14621 , H01L27/14627 , H01L27/14634 , H01L27/14683 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/13 , H01L2224/45144 , H01L2224/48091 , H01L2924/16235 , H05K3/323 , H05K3/361 , H05K2201/0367 , Y10T29/49144 , H01L2924/00014 , H01L2924/00
摘要： A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a flexible wiring substrate having at least one contact section being electrically connected with the bump by the adhesive layer. The present invention makes the flexible wiring substrate directly conductively attached onto the semiconductor substrate. The package size is shrunk and the cost down can be obtained.
摘要翻译：提供具有柔性布线基板的半导体器件的封装及其方法。该半导体器件的封装包括：半导体衬底，其表面上具有至少一个衬垫，与焊盘接合的凸块，凸块上的粘合剂层;以及柔性布线衬底，具有至少一个接触部分与由粘合剂层撞击。本发明使柔性布线基板直接导电地附着在半导体基板上。包装尺寸缩小，可以降低成本。

3. 发明申请

US20050161756A1 Package of a semiconductor device with a flexible wiring substrate and method for the same 有权
标题翻译：具有柔性布线基板的半导体器件的封装及其方法
公开(公告)号：US20050161756A1
公开(公告)日：2005-07-28
申请号：US11050814
申请日：2005-01-27
申请人： Joseph Sun , Kuang-Chih Cheng , Ming-Chieh Chen , Kevin Lee , Jui-Hsiang Pan
发明人： Joseph Sun , Kuang-Chih Cheng , Ming-Chieh Chen , Kevin Lee , Jui-Hsiang Pan
IPC分类号： H01L21/00 , H01L21/48 , H01L23/48 , H01L23/498 , H01L27/146 , H01L31/0203 , H05K3/32 , H05K3/36
CPC分类号： H01L27/14618 , H01L23/49816 , H01L23/4985 , H01L27/14621 , H01L27/14627 , H01L27/14634 , H01L27/14683 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/13 , H01L2224/45144 , H01L2224/48091 , H01L2924/16235 , H05K3/323 , H05K3/361 , H05K2201/0367 , Y10T29/49144 , H01L2924/00014 , H01L2924/00
摘要： A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a flexible wiring substrate having at least one contact section being electrically connected with the bump by the adhesive layer. The present invention makes the flexible wiring substrate directly conductively attached onto the semiconductor substrate. The package size is shrunk and the cost down can be obtained.
摘要翻译：提供具有柔性布线基板的半导体器件的封装及其方法。该半导体器件的封装包括：半导体衬底，其表面上具有至少一个衬垫，与焊盘接合的凸块，凸块上的粘合剂层;以及柔性布线衬底，具有至少一个接触部分与由粘合剂层撞击。本发明使柔性布线基板直接导电地附着在半导体基板上。包装尺寸缩小，可以降低成本。

4. 发明申请

US20060057764A1 IMAGE SENSOR AND FABRICATING METHOD THEREOF 有权
标题翻译：图像传感器及其制作方法
公开(公告)号：US20060057764A1
公开(公告)日：2006-03-16
申请号：US10711377
申请日：2004-09-15
申请人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Shin Lee
发明人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Shin Lee
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer and the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.
摘要翻译：提供了包括图像感测装置层，绝缘体上硅（SOI）层，光学装置阵列和基板的图像传感器。 SOI层具有第一表面和第二表面。图像感测装置层形成在SOI层的第一表面上。光学器件阵列形成在SOI层的第二表面上。衬底设置在SOI层的第二表面上方，并且光学器件阵列设置在衬底和SOI层之间。来自外部环境的入射光通过光学器件阵列和SOI层，并且由形成在图像感测器件层中的感测器件接收。以这种方式，入射光的吸收或反射的概率降低。因此，提高了本发明的图像传感器的感测性能和产量。

5. 发明申请

US20060180860A1 IMAGE SENSOR 审中-公开
标题翻译：图像传感器
公开(公告)号：US20060180860A1
公开(公告)日：2006-08-17
申请号：US11308330
申请日：2006-03-16
申请人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Hsing Lee
发明人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Hsing Lee
IPC分类号： H01L27/12
CPC分类号： H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： An image sensor including an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer; the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.
摘要翻译：提供了包括图像感测装置层，绝缘体上硅层（SOI）层，光学装置阵列和基板的图像传感器。 SOI层具有第一表面和第二表面。图像感测装置层形成在SOI层的第一表面上。光学器件阵列形成在SOI层的第二表面上。衬底设置在SOI层的第二表面上方; 光学器件阵列设置在衬底和SOI层之间。来自外部环境的入射光通过光学器件阵列和SOI层，并且由形成在图像感测器件层中的感测器件接收。以这种方式，入射光的吸收或反射的概率降低。因此，提高了本发明的图像传感器的感测性能和产量。

6. 发明授权

US07060592B2 Image sensor and fabricating method thereof 有权
标题翻译：图像传感器及其制造方法
公开(公告)号：US07060592B2
公开(公告)日：2006-06-13
申请号：US10711377
申请日：2004-09-15
申请人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Shin Lee
发明人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Shin Lee
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer and the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.
摘要翻译：提供了包括图像感测装置层，绝缘体上硅（SOI）层，光学装置阵列和基板的图像传感器。 SOI层具有第一表面和第二表面。图像感测装置层形成在SOI层的第一表面上。光学器件阵列形成在SOI层的第二表面上。衬底设置在SOI层的第二表面上方，并且光学器件阵列设置在衬底和SOI层之间。来自外部环境的入射光通过光学器件阵列和SOI层，并且由形成在图像感测器件层中的感测器件接收。以这种方式，入射光的吸收或反射的概率降低。因此，提高了本发明的图像传感器的感测性能和产量。

7. 发明授权

US07531381B2 Manufacturing method of a quad flat no-lead package structure 有权
标题翻译：四边形无引线封装结构的制造方法
公开(公告)号：US07531381B2
公开(公告)日：2009-05-12
申请号：US11307872
申请日：2006-02-26
申请人： Jui-Hsiang Pan , Kuang-Shin Lee , Cheng-Kuang Sun
发明人： Jui-Hsiang Pan , Kuang-Shin Lee , Cheng-Kuang Sun
IPC分类号： H01L21/00
CPC分类号： H01L23/49827 , H01L24/45 , H01L24/48 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： The present invention provides a method for fabricating a quad flat no-lead package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.
摘要翻译：本发明提供一种制造四边形扁平无引线封装结构的方法，其包括芯片载体和至少芯片。芯片设置在芯片载体的顶表面上，而芯片载体的背面包括多个平坦的无导线导线作为用于外部电路的芯片载体的I / O焊盘。对应于芯片的接合焊盘的多个焊盘设置在芯片载体的顶表面上。上述封装结构可以采用布线接合技术，倒装芯片技术或表面贴装技术将芯片附接到芯片载体。

8. 发明授权

US06373121B1 Silicon chip built-in inductor structure 有权
标题翻译：硅芯片内置电感结构
公开(公告)号：US06373121B1
公开(公告)日：2002-04-16
申请号：US09815861
申请日：2001-03-23
申请人： Jui-Hsiang Pan
发明人： Jui-Hsiang Pan
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01L27/0688 , H01L27/08
摘要： A silicon chip built-in inductor structure. The structure at least includes a substrate, a plurality of active devices on the substrate, a dielectric layer with a planarized upper surface and an inductor device. The substrate can be divided into an active device region and a region containing grid-like field oxide devices. The grid-like field oxide region has a plurality of field oxide layers, a plurality of first-type-ion-doped regions underneath the field oxide layers and a plurality of second-type-ion-doped region in the substrate between the various field oxide layers. A plurality of junction regions are formed between the first-type-ion-doped regions and the second-type-ion-doped regions. The junction regions impede the flow of an eddy current along a prescribed direction. A dielectric layer is formed over the substrate covering the active devices and the field oxide devices. The inductor device is formed on the dielectric layer above the field oxide devices.
摘要翻译：硅芯片内置电感结构。该结构至少包括衬底，衬底上的多个有源器件，具有平坦化上表面的电介质层和电感器器件。衬底可以分为有源器件区域和包含格栅状场氧化物器件的区域。格栅状场氧化物区域具有多个场氧化物层，在场氧化物层下面的多个第一离子掺杂区域和在各种场之间的衬底中的多个第二离子掺杂区域氧化层。在第一类型离子掺杂区域和第二类型离子掺杂区域之间形成多个结区域。连接区域沿着规定的方向阻止涡流的流动。在覆盖有源器件和场氧化物器件的衬底上形成介电层。电感器件形成在场氧化物器件上方的电介质层上。

9. 发明授权

US06271553B1 Photo sensor in a photo diode 有权
标题翻译：光电二极管中的光电传感器
公开(公告)号：US06271553B1
公开(公告)日：2001-08-07
申请号：US09450021
申请日：1999-11-29
申请人： Jui-Hsiang Pan
发明人： Jui-Hsiang Pan
IPC分类号： H01L31062
CPC分类号： H01L27/14609 , H01L27/1463
摘要： The surface of a semiconductor wafer comprises a silicon substrate and a well positioned in a predetermined area just under the surface of the substrate. A photo diode comprises a MOS transistor positioned on the surface of the well, a photo sensor positioned beside the well and electrically connected to the MOS transistor, and an insulation layer positioned on the surface of the substrate surrounding the photo sensor. The photo sensor comprises a first doped region positioned on the surface of the photo sensor, and a second doped region positioned between the first doped region and the insulation layer, a portion of the second doped region at least partially under the insulation layer. The dopant density of the second doped region is less than that of the first doped region, and the second doped region functions to reduce the electrical field around the first doped region so as to reduce the leakage current.
摘要翻译：半导体晶片的表面包括硅衬底和阱位于衬底表面正下方的预定区域中。光电二极管包括位于阱的表面上的MOS晶体管，位于阱旁边并电连接到MOS晶体管的光电传感器，以及位于围绕光传感器的基板的表面上的绝缘层。光传感器包括位于光传感器表面上的第一掺杂区域和位于第一掺杂区域和绝缘层之间的第二掺杂区域，第二掺杂区域的至少部分地位于绝缘层下方的部分。第二掺杂区域的掺杂剂密度小于第一掺杂区域的掺杂浓度，第二掺杂区域用于减小第一掺杂区域周围的电场，从而减少漏电流。

10. 发明授权

US6150189A Method for forming a photo diode and a CMOS transistor simultaneously 有权
标题翻译：同时形成光电二极管和CMOS晶体管的方法
公开(公告)号：US6150189A
公开(公告)日：2000-11-21
申请号：US391358
申请日：1999-09-08
申请人： Jui-Hsiang Pan
发明人： Jui-Hsiang Pan
IPC分类号： H01L27/06 , H01L27/146 , H01L21/00
CPC分类号： H01L27/0629 , H01L27/14609 , H01L27/1463 , H01L27/14632
摘要： This invention provides a method of simultaneously forming a photo diode and a CMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a P-type substrate. The surface of the P-type substrate comprises at least one N-channel MOS area for forming an NMOS transistor of the CMOS transistor, a P-channel MOS area for forming a PMOS transistor of the CMOS transistor, and a photo sensing area for forming a photo diode. The method comprises an ion implantation process to form a P-type well in the NMOS area, and an ion implantation process to form a N-type doped area in a predetermined area on the surface of the photo sensing area and also to form a N-type well of the PMOS transistor in the PMOS area. The dopants in the N-type doped area will interact with the neighboring P-type substrate to form a depletion region which fills the P-type substrate within the photo sensing area but outside the predetermined area. Thus, the surface of the photo sensing area is completely covered by the N-type doped area and the depletion region.
摘要翻译：本发明提供了一种在半导体晶片上同时形成光电二极管和CMOS晶体管的方法。半导体晶片包括P型衬底。 P型衬底的表面包括用于形成CMOS晶体管的NMOS晶体管的至少一个N沟道MOS区域，用于形成CMOS晶体管的PMOS晶体管的P沟道MOS区域和用于形成一个光电二极管。该方法包括在NMOS区域中形成P型阱的离子注入工艺，以及离子注入工艺，以在光敏区域的表面上的预定区域中形成N型掺杂区域，并且还形成N 在PMOS区域中的PMOS晶体管的类型阱。 N型掺杂区域中的掺杂剂将与相邻的P型衬底相互作用以形成耗尽区，其填充光感测区内的P型衬底，但在预定区域之外。因此，光感测区域的表面完全被N型掺杂区域和耗尽区域覆盖。

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