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1. 发明申请

US20160147858A1 Log Forwarding to Avoid Deadlocks During Parallel Log Replay in Asynchronous Table Replication 有权
标题翻译：日志转发以避免在异步表复制期间的并行日志重放期间的死锁
公开(公告)号：US20160147858A1
公开(公告)日：2016-05-26
申请号：US14657854
申请日：2015-03-13
申请人： Juchang Lee , Chang-Gyoo Park , Hyoung-Jun Na , Deok-Hoe Kim
发明人： Juchang Lee , Chang-Gyoo Park , Hyoung-Jun Na , Deok-Hoe Kim
IPC分类号： G06F17/30
CPC分类号： G06F11/1469 , G06F11/1464 , G06F17/30368 , G06F17/30371 , G06F17/30377 , G06F17/30575 , G06F17/30578 , G06F17/30876 , G06F2201/80
摘要： Disclosed herein are system, method, and computer program product embodiments for removing a deadlock during replication from distributed source tables to a replica node. An embodiment operates by detecting a deadlock at a parallel log replayer at a replica node. A first replication log entry from a queue at the parallel log replayer is then selected based on whether removing the first replication log entry from the queue removes the deadlock. The first replication log entry is then forwarded to a waiting queue. A second replication log entry is then replayed at the parallel log replayer. After replaying the second replication log entry, the first replication log entry is replayed at the parallel log replayer.
摘要翻译：这里公开了用于在从分布式源表复制到复制节点的过程中去除死锁的系统，方法和计算机程序产品实施例。实施例通过检测复制节点处的并行日志重播器处的死锁而进行操作。然后根据是否从队列中删除第一个复制日志条目来删除死锁，来选择并行日志重播器中队列中的第一个复制日志条目。然后将第一个复制日志条目转发到等待队列。然后在并行日志重播器中重播第二个复制日志条目。重播第二个复制日志条目后，第一个复制日志条目将在并行日志重播器中重播。

2. 发明授权

US09965359B2 Log forwarding to avoid deadlocks during parallel log replay in asynchronous table replication 有权
公开(公告)号：US09965359B2
公开(公告)日：2018-05-08
申请号：US14657854
申请日：2015-03-13
申请人： Juchang Lee , Chang-Gyoo Park , Hyoung-Jun Na , Deok-Hoe Kim
发明人： Juchang Lee , Chang-Gyoo Park , Hyoung-Jun Na , Deok-Hoe Kim
IPC分类号： G06F17/30 , G06F11/14
CPC分类号： G06F11/1469 , G06F11/1464 , G06F17/30368 , G06F17/30371 , G06F17/30377 , G06F17/30575 , G06F17/30578 , G06F17/30876 , G06F2201/80
摘要： Disclosed herein are system, method, and computer program product embodiments for removing a deadlock during replication from distributed source tables to a replica node. An embodiment operates by detecting a deadlock at a parallel log replayer at a replica node. A first replication log entry from a queue at the parallel log replayer is then selected based on whether removing the first replication log entry from the queue removes the deadlock. The first replication log entry is then forwarded to a waiting queue. A second replication log entry is then replayed at the parallel log replayer. After replaying the second replication log entry, the first replication log entry is replayed at the parallel log replayer.

3. 发明申请

US20160147859A1 Transactional and Parallel Log Replay for Asynchronous Table Replication 有权
标题翻译：异步表复制的事务和并行日志重放
公开(公告)号：US20160147859A1
公开(公告)日：2016-05-26
申请号：US14657948
申请日：2015-03-13
申请人： Juchang Lee , Chang-Gyoo Park , Hyoung-Jun Na , Kyu-Hwan Kim
发明人： Juchang Lee , Chang-Gyoo Park , Hyoung-Jun Na , Kyu-Hwan Kim
IPC分类号： G06F17/30
CPC分类号： G06F11/1469 , G06F11/1464 , G06F17/30368 , G06F17/30371 , G06F17/30377 , G06F17/30575 , G06F17/30578 , G06F17/30876 , G06F2201/80
摘要： Disclosed herein are system, method, and computer program product embodiments for replicating a database transaction to a replica table. An embodiment operates by receiving a replication log entry and an associated transaction commit log entry for a database transaction to be replayed to a row at a replica table. A row-ID value of the replication log entry is compared to a row-ID column value of the row at the replica table. The replication log entry is then replayed at a parallel log replayer based on the comparison. The database transaction is then committed to the replica table by replaying the associated transaction commit log entry at a transaction log replayer.
摘要翻译：这里公开了用于将数据库事务复制到副本表的系统，方法和计算机程序产品实施例。一个实施例通过接收复制日志条目和相关联的事务提交日志条目来进行操作，以便数据库事务被重播到副本表的行。将复制日志条目的行ID值与副本表中的行的行ID列值进行比较。然后，基于比较，在并行日志重播器中重播复制日志条目。然后，数据库事务通过在事务日志重播器上重播关联的事务提交日志条目来提交给副本表。

4. 发明申请

US20120221750A1 DATA TRANSFER CIRCUIT AND MEMORY DEVICE HAVING THE SAME 有权
标题翻译：数据传输电路和具有该数据传输电路的存储器件
公开(公告)号：US20120221750A1
公开(公告)日：2012-08-30
申请号：US13329865
申请日：2011-12-19
申请人： Hyoung-Jun Na , Jae-Il Kim
发明人： Hyoung-Jun Na , Jae-Il Kim
IPC分类号： G06F13/00
CPC分类号： G11C7/1012 , G06F13/1668 , G11C7/1087 , G11C2207/107
摘要： A data transfer circuit includes a serial-to-parallel converter configured to convert multi-bit data inputted in series into parallel data by controlling the number of bits of the parallel data and a conversion timing based on an operation mode, and a data transmission unit configured to transfer the parallel data to a first data path or a second data path based on the operation mode.
摘要翻译：数据传输电路包括串并转换器，其被配置为通过控制并行数据的位数和基于操作模式的转换定时将串行输入的多位数据转换为并行数据，以及数据传输单元被配置为基于所述操作模式将并行数据传送到第一数据路径或第二数据路径。

5. 发明授权

US08924679B2 Memory device and memory system including the same 有权
标题翻译：存储器件和存储器系统包括相同的
公开(公告)号：US08924679B2
公开(公告)日：2014-12-30
申请号：US13204937
申请日：2011-08-08
申请人： Hyoung-Jun Na , Jae-Il Kim
发明人： Hyoung-Jun Na , Jae-Il Kim
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00 , G06F13/28
CPC分类号： G06F12/00 , G06F12/0607 , G06F13/00 , G06F13/28 , G11C2207/107 , G11C2207/2281
摘要： A memory device includes a first bank group, a second bank group, where the first and second bank groups are each configured to output multi-bit data in parallel in response to a read command, a data transferor configured to receive the multi-bit data outputted in parallel from the first bank group or the second bank group and output the multi-bit data at a time interval corresponding to an operation mode, first global data buses configured to transfer the multi-bit data outputted from the first bank group to the data transferor, second global data buses configured to transfer the multi-bit data outputted from the second bank group to the data transferor, and a parallel-to-serial converter configured to convert the multi-bit data outputted from the data transferor into serial data according to the operation mode.
摘要翻译：存储器件包括第一组组，第二组组，其中第一组组和第二组组各自被配置为响应于读取命令并行输出多位数据;数据传送器，被配置为接收多位数据从第一组组或第二组组并行输出，并以对应于操作模式的时间间隔输出多位数据，第一全局数据总线被配置为将从第一组组输出的多位数据传送到数据传送器，被配置为将从第二组组输出的多位数据传送到数据传送器的第二全局数据总线;以及并行到串行转换器，其被配置为将从数据传送器输出的多位数据转换成串行数据根据操作模式。

6. 发明授权

US08350613B2 Signal delay circuit, clock transfer control circuit and semiconductor device having the same 有权
标题翻译：信号延迟电路，时钟传输控制电路和具有该信号的半导体器件
公开(公告)号：US08350613B2
公开(公告)日：2013-01-08
申请号：US13552037
申请日：2012-07-18
申请人： Hyoung-Jun Na , Kyung-Whan Kim
发明人： Hyoung-Jun Na , Kyung-Whan Kim
IPC分类号： G06F1/04
CPC分类号： H03K5/04
摘要： A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal.
摘要翻译：一种信号延迟电路，包括被配置为发送或阻断时钟信号的时钟传送控制电路，以及脉冲信号生成电路，被配置为响应于发送的时钟信号而延迟第一脉冲信号，以产生具有较长活动的第二脉冲信号周期比第一脉冲信号。

7. 发明申请

US20100315157A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100315157A1
公开(公告)日：2010-12-16
申请号：US12494681
申请日：2009-06-30
申请人： Hyoung-Jun Na , Kyung-Whan Kim
发明人： Hyoung-Jun Na , Kyung-Whan Kim
IPC分类号： G05F3/02 , G05F1/10
CPC分类号： G05F1/465 , G05F1/56
摘要： A semiconductor device is capable of generating an internal voltage having a voltage level that is dependent on an external power supply voltage. The semiconductor device includes an internal voltage generation unit configured to generate a plurality of internal voltages having different voltage levels by using an external power supply voltage, a voltage level detection unit configured to detect a voltage level of the external power supply voltage, and a selection unit configured to selectively output one of the internal voltages in response to a detection result of the voltage level detection unit.
摘要翻译：半导体器件能够产生具有取决于外部电源电压的电压电平的内部电压。半导体器件包括：内部电压生成单元，被配置为通过使用外部电源电压生成具有不同电压电平的多个内部电压;电压电平检测单元，被配置为检测外部电源电压的电压电平;以及选择单元，被配置为响应于电压电平检测单元的检测结果选择性地输出内部电压之一。

8. 发明授权

US08922273B2 Internal voltage generator 有权
标题翻译：内部电压发生器
公开(公告)号：US08922273B2
公开(公告)日：2014-12-30
申请号：US12494681
申请日：2009-06-30
申请人： Hyoung-Jun Na , Kyung-Whan Kim
发明人： Hyoung-Jun Na , Kyung-Whan Kim
IPC分类号： G05F1/10 , G05F1/56
CPC分类号： G05F1/465 , G05F1/56
摘要： A semiconductor device is capable of generating an internal voltage having a voltage level that is dependent on an external power supply voltage. The semiconductor device includes an internal voltage generation unit configured to generate a plurality of internal voltages having different voltage levels by using an external power supply voltage, a voltage level detection unit configured to detect a voltage level of the external power supply voltage, and a selection unit configured to selectively output one of the internal voltages in response to a detection result of the voltage level detection unit.
摘要翻译：半导体器件能够产生具有取决于外部电源电压的电压电平的内部电压。半导体器件包括：内部电压生成单元，被配置为通过使用外部电源电压生成具有不同电压电平的多个内部电压;电压电平检测单元，被配置为检测外部电源电压的电压电平;以及选择单元，被配置为响应于电压电平检测单元的检测结果选择性地输出内部电压之一。

9. 发明授权

US08745288B2 Data transfer circuit and memory device having the same 有权
标题翻译：数据传输电路和存储器件具有相同的功能
公开(公告)号：US08745288B2
公开(公告)日：2014-06-03
申请号：US13329865
申请日：2011-12-19
申请人： Hyoung-Jun Na , Jae-Il Kim
发明人： Hyoung-Jun Na , Jae-Il Kim
IPC分类号： G06F13/00 , G06F13/38
CPC分类号： G11C7/1012 , G06F13/1668 , G11C7/1087 , G11C2207/107
摘要： A data transfer circuit includes a serial-to-parallel converter configured to convert multi-bit data inputted in series into parallel data by controlling the number of bits of the parallel data and a conversion timing based on an operation mode, and a data transmission unit configured to transfer the parallel data to a first data path or a second data path based on the operation mode.
摘要翻译：数据传输电路包括串并转换器，其被配置为通过控制并行数据的位数和基于操作模式的转换定时将串行输入的多位数据转换为并行数据，以及数据传输单元被配置为基于所述操作模式将并行数据传送到第一数据路径或第二数据路径。

10. 发明授权

US08248129B2 Signal delay circuit, clock transfer control circuit and semiconductor device having the same 有权
标题翻译：信号延迟电路，时钟传输控制电路和具有该信号的半导体器件
公开(公告)号：US08248129B2
公开(公告)日：2012-08-21
申请号：US12792530
申请日：2010-06-02
申请人： Hyoung-Jun Na , Kyung-Whan Kim
发明人： Hyoung-Jun Na , Kyung-Whan Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/04
摘要： A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal.
摘要翻译：一种信号延迟电路，包括被配置为发送或阻断时钟信号的时钟传送控制电路，以及脉冲信号生成电路，被配置为响应于发送的时钟信号而延迟第一脉冲信号，以产生具有较长活动的第二脉冲信号周期比第一脉冲信号。

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