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1. 发明申请

US20060031798A1 Special engineering change order cells 失效
公开(公告)号：US20060031798A1
公开(公告)日：2006-02-09
申请号：US10897655
申请日：2004-07-22
申请人： Juergen Dirks , Matthias Dinter , Johann Leyrer
发明人： Juergen Dirks , Matthias Dinter , Johann Leyrer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.

2. 发明申请

US20100050142A1 SPECIAL ENGINEERING CHANGE ORDER CELLS 失效
标题翻译：特殊工程变更订单细胞
公开(公告)号：US20100050142A1
公开(公告)日：2010-02-25
申请号：US12608469
申请日：2009-10-29
申请人： Juergen Dirks , Matthias Dinter , Johann Leyrer
发明人： Juergen Dirks , Matthias Dinter , Johann Leyrer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.
摘要翻译：公开了一种用于校正电路设计中的多个违规的方法和用于该方法的新单元。该方法通常包括以下步骤：（A）在电路设计中实施第一工程变更顺序以纠正第一违规行为，（B）用专用小区实施第二工程变更单以纠正第二个违规行为，具有可用于与第二违例相关联的信号路径的多个接口的特殊小区，每个接口具有适于校正第二违例的特性，每个特性具有不同的性能，（C）将信号路径路由到一个的接口来修复第二次违规。

3. 发明授权

US08332801B2 Special engineering change order cells 失效
标题翻译：特殊工程变更订单单元格
公开(公告)号：US08332801B2
公开(公告)日：2012-12-11
申请号：US12608469
申请日：2009-10-29
申请人： Juergen Dirks , Matthias Dinter , Johann Leyrer
发明人： Juergen Dirks , Matthias Dinter , Johann Leyrer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.
摘要翻译：公开了一种用于校正电路设计中的多个违规的方法和用于该方法的新单元。该方法通常包括以下步骤：（A）在电路设计中实施第一工程变更顺序以纠正第一违规行为，（B）用专用小区实施第二工程变更单以纠正第二个违规行为，具有可用于与第二违例相关联的信号路径的多个接口的特殊小区，每个接口具有适于校正第二违例的特性，每个特性具有不同的性能，（C）将信号路径路由到一个的接口来修复第二次违规。

4. 发明授权

US07634748B2 Special engineering change order cells 失效
标题翻译：特殊工程变更订单单元格
公开(公告)号：US07634748B2
公开(公告)日：2009-12-15
申请号：US10897655
申请日：2004-07-22
申请人： Juergen Dirks , Matthias Dinter , Johann Leyrer
发明人： Juergen Dirks , Matthias Dinter , Johann Leyrer
IPC分类号： G06F17/50 , G06F9/45 , H03K17/693
CPC分类号： G06F17/5045
摘要： A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.
摘要翻译：公开了一种用于校正电路设计中的多个违规的方法和用于该方法的新单元。该方法通常包括以下步骤：（A）在电路设计中实施第一工程变更顺序以纠正第一违规行为，（B）用专用小区实施第二工程变更单以纠正第二个违规行为，具有可用于与第二违例相关联的信号路径的多个接口的特殊小区，每个接口具有适于校正第二违例的特性，每个特性具有不同的性能，（C）将信号路径路由到一个的接口来修复第二次违规。

5. 发明申请

US20060119420A1 On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method 有权
标题翻译：片上自动过程变化，电源电压变化和温度偏差（PVT）补偿方法
公开(公告)号：US20060119420A1
公开(公告)日：2006-06-08
申请号：US11004415
申请日：2004-12-03
申请人： Weidan Li , Benjamin Mbouombouo , Johann Leyrer
发明人： Weidan Li , Benjamin Mbouombouo , Johann Leyrer
IPC分类号： G05F1/10
CPC分类号： H03K3/0315
摘要： An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillators. An output of the multiplexer is connected to a comparator, such as a phase detector. The comparator also receives an output from a PLL, and is configured to compare the output of the multiplexer to the output of the PLL. An output of the comparator is connected to the controllable voltage regulator. The controllable voltage regulator receives a voltage in as well as the output of the comparator, and applies a substrate bias depending on what is received from the comparator.
摘要翻译：片上基板电压控制器，其包括连接到多路复用器的多个互连的加载环形振荡器的链，其中多路复用器被配置为平均来自互连加载的环形振荡器的所有链的输出。多路复用器的输出端连接到诸如相位检测器的比较器。比较器还接收来自PLL的输出，并且被配置为将多路复用器的输出与PLL的输出进行比较。比较器的输出端连接到可控电压调节器。可控电压调节器接收比较器的电压以及比较器的输出，并根据从比较器接收的内容施加衬底偏置。

6. 发明授权

US07334207B2 Automatic placement based ESD protection insertion 失效
标题翻译：基于自动放置的ESD保护插入
公开(公告)号：US07334207B2
公开(公告)日：2008-02-19
申请号：US11140896
申请日：2005-05-31
申请人： Herbert Johannes Preuthen , Johann Leyrer , Hermann Sauter
发明人： Herbert Johannes Preuthen , Johann Leyrer , Hermann Sauter
IPC分类号： G06F17/50
CPC分类号： H01L27/0251 , H01L27/0292
摘要： An apparatus comprising a plurality of input cells, two or more local tie up cells, and two or more local tie down cells. The plurality of input cells may be configured to provide (i) one or more gate voltage signals and (ii) one or more supply voltage signals. The two or more local tie up cells may be configured to provide electrostatic discharge (ESD) protection to one or more first standard cells. Each of the local tie up cells may be coupled to (i) the one or more first standard cells and (ii) each of the gate voltage signals. The two or more local tie down cells may be configured to provide ESD protection to one or more second standard cells. Each of the local tie down cells may be coupled to (i) the one or more second standard cells and (ii) each of the supply voltage signals.
摘要翻译：一种装置，包括多个输入单元，两个或多个局部连接单元以及两个或多个局部闭合单元。多个输入单元可以被配置为提供（i）一个或多个栅极电压信号和（ii）一个或多个电源电压信号。两个或多个局部连接单元可以被配置为向一个或多个第一标准单元提供静电放电（ESD）保护。每个局部连接单元可以耦合到（i）一个或多个第一标准单元和（ii）每个栅极电压信号。两个或多个本地绑定单元可以被配置为向一个或多个第二标准单元提供ESD保护。每个本地绑定单元可以耦合到（i）一个或多个第二标准单元和（ii）每个电源电压信号。

7. 发明申请

US20060268486A1 Automatic placement based ESD protection insertion 失效
标题翻译：基于自动放置的ESD保护插入
公开(公告)号：US20060268486A1
公开(公告)日：2006-11-30
申请号：US11140896
申请日：2005-05-31
申请人： Herbert Preuthen , Johann Leyrer , Hermann Sauter
发明人： Herbert Preuthen , Johann Leyrer , Hermann Sauter
IPC分类号： H02H7/20
CPC分类号： H01L27/0251 , H01L27/0292
摘要： An apparatus comprising a plurality of input cells, two or more local tie up cells, and two or more local tie down cells. The plurality of input cells may be configured to provide (i) one or more gate voltage signals and (ii) one or more supply voltage signals. The two or more local tie up cells may be configured to provide electrostatic discharge (ESD) protection to one or more first standard cells. Each of the local tie up cells may be coupled to (i) the one or more first standard cells and (ii) each of the gate voltage signals. The two or more local tie down cells may be configured to provide ESD protection to one or more second standard cells. Each of the local tie down cells may be coupled to (i) the one or more second standard cells and (ii) each of the supply voltage signals.
摘要翻译：一种装置，包括多个输入单元，两个或多个局部连接单元以及两个或多个局部闭合单元。多个输入单元可以被配置为提供（i）一个或多个栅极电压信号和（ii）一个或多个电源电压信号。两个或多个局部连接单元可以被配置为向一个或多个第一标准单元提供静电放电（ESD）保护。每个局部连接单元可以耦合到（i）一个或多个第一标准单元和（ii）每个栅极电压信号。两个或多个本地绑定单元可以被配置为向一个或多个第二标准单元提供ESD保护。每个本地绑定单元可以耦合到（i）一个或多个第二标准单元和（ii）每个电源电压信号。

8. 发明授权

US06532577B1 Timing driven interconnect analysis 有权
标题翻译：定时驱动互连分析
公开(公告)号：US06532577B1
公开(公告)日：2003-03-11
申请号：US09894618
申请日：2001-06-27
申请人： Benjamin Mbouombouo , Johann Leyrer , Human Boluki
发明人： Benjamin Mbouombouo , Johann Leyrer , Human Boluki
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method for performing timing driven interconnect estimation analysis is disclosed. The method includes collecting data only from timing critical paths of at least one previous design, and generating statistical data based on a net length distribution of the timing critical paths. A wire load model is then generated for a new design from the statistical data.
摘要翻译：公开了一种用于执行定时驱动的互连估计分析的方法。该方法包括仅从至少一个先前设计的定时关键路径收集数据，以及基于定时关键路径的净长度分布生成统计数据。然后从统计数据为新设计生成有线负载模型。

9. 发明授权

US06788098B1 Test structures for simultaneous switching output (SSO) analysis 失效
标题翻译：用于同时开关输出（SSO）分析的测试结构
公开(公告)号：US06788098B1
公开(公告)日：2004-09-07
申请号：US10414703
申请日：2003-04-16
申请人： Alaa A. Alani , Johann Leyrer , Human Boluki
发明人： Alaa A. Alani , Johann Leyrer , Human Boluki
IPC分类号： H03K1900
CPC分类号： H04L25/14
摘要： An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of intermediate signals from a data signal. Each of the intermediate signals may be switchable between (i) a common delay and (ii) one of a plurality of different staggered delays determined by a stagger signal. The a second circuit may be configured to generate a plurality of first drive signals by gating the intermediate signals with a plurality of enable signals. The a third circuit may be configured to generate a plurality of first output signals at a transmit interface of a chip by buffering the first drive signals.
摘要翻译：公开了一种包括第一电路，第二电路和第三电路的装置。第一电路可以被配置为从数据信号产生多个中间信号。每个中间信号可以在（i）公共延迟和（ii）由交错信号确定的多个不同交错延迟中的一个之间切换。第二电路可以被配置为通过利用多个使能信号门控中间信号来产生多个第一驱动信号。第三电路可以被配置为通过缓冲第一驱动信号在芯片的发送接口处产生多个第一输出信号。

10. 发明授权

US06608365B1 Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells 有权
标题翻译：低泄漏PMOS片上去耦电容电池与标准CMOS电池兼容
公开(公告)号：US06608365B1
公开(公告)日：2003-08-19
申请号：US10163120
申请日：2002-06-04
申请人： Weidan Li , Benjamin Mbouombouo , Johann Leyrer
发明人： Weidan Li , Benjamin Mbouombouo , Johann Leyrer
IPC分类号： H01L2900
CPC分类号： H01L27/0811 , H01L29/94
摘要： An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.
摘要翻译：公开了与标准CMOS电池兼容的片上去耦电容器单元。限定单元的区域的单元边界包括第一晶体管区域和第二晶体管区域。具有n阱的PMOS晶体管形成在第一晶体管区域内。片上去耦电容器单元还包括将n阱扩展到第二晶体管区域中的n阱延伸，从而提供与CMOS电容器单元相比具有减小的泄漏的去耦电容器单元，并且与单位面积相比增加了每单位面积的电容一个传统的PMOS电容单元。

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