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1. 发明申请

US20090271133A1 CLOCK JITTER MEASUREMENT CIRCUIT AND INTEGRATED CIRCUIT HAVING THE SAME 有权
标题翻译：时钟抖动测量电路和集成电路
公开(公告)号：US20090271133A1
公开(公告)日：2009-10-29
申请号：US12108796
申请日：2008-04-24
申请人： Jung-Chi Ho , Sheng-Bin Lin , Yeong-Jar Chang
发明人： Jung-Chi Ho , Sheng-Bin Lin , Yeong-Jar Chang
IPC分类号： G01R23/00
CPC分类号： G01R29/26 , G01R31/3016 , G01R31/31709
摘要： Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.
摘要翻译：提供了一种用于测量时钟信号的抖动的测量电路。延迟元件将时钟信号延迟到延迟的时钟信号。锁存器锁存延迟的时钟信号以指示时钟信号的转换边沿是否在对应于延迟元件的延迟的窗口值内。基于锁存器的锁存结果，有限状态机产生用于控制延迟元件的控制信号。如果锁存结果指示时钟信号的转换边缘不在窗口值内，则控制信号调整延迟元件的延迟和窗口值。基于延迟元件的延迟和窗口值来测量时钟信号的抖动。

2. 发明授权

US07945404B2 Clock jitter measurement circuit and integrated circuit having the same 有权
标题翻译：时钟抖动测量电路和集成电路相同
公开(公告)号：US07945404B2
公开(公告)日：2011-05-17
申请号：US12108796
申请日：2008-04-24
申请人： Jung-Chi Ho , Sheng-Bin Lin , Yeong-Jar Chang
发明人： Jung-Chi Ho , Sheng-Bin Lin , Yeong-Jar Chang
IPC分类号： G01R23/00 , G06F19/00
CPC分类号： G01R29/26 , G01R31/3016 , G01R31/31709
摘要： Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.
摘要翻译：提供了一种用于测量时钟信号的抖动的测量电路。延迟元件将时钟信号延迟到延迟的时钟信号。锁存器锁存延迟的时钟信号以指示时钟信号的转换边沿是否在对应于延迟元件的延迟的窗口值内。基于锁存器的锁存结果，有限状态机产生用于控制延迟元件的控制信号。如果锁存结果指示时钟信号的转换边缘不在窗口值内，则控制信号调整延迟元件的延迟和窗口值。基于延迟元件的延迟和窗口值来测量时钟信号的抖动。

3. 发明申请

US20100031206A1 METHOD AND TECHNIQUE FOR ANALOGUE CIRCUIT SYNTHESIS 审中-公开
标题翻译：模拟电路合成的方法与技术
公开(公告)号：US20100031206A1
公开(公告)日：2010-02-04
申请号：US12512086
申请日：2009-07-30
申请人： Chang-Chung Wu , Chi-Che Chen , Jung-Chi Ho , Woei-Tzy Jong , Yeong-Jar Chang
发明人： Chang-Chung Wu , Chi-Che Chen , Jung-Chi Ho , Woei-Tzy Jong , Yeong-Jar Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5063
摘要： Method and technique for analogue circuit synthesis. An analogue circuit usually includes many circuit components, and characteristics and functions of each circuit component are controlled by many corresponding parameters. In the presented invention, selected key design parameters of selected critical circuit components, as well as optimization targets, design specification or/and design constraint, are transformed into an optimization plan, and an optimization engine iterates circuit level or system level numerical simulations by changing values of the selected key design parameters recorded in the optimization plan, so as to find optimized parameters and circuit components which allow the analogue circuit to match the design specification/constraint and to approach the optimization target. Thus a systematic automation for analogue circuit synthesis/design/optimization is achieved.
摘要翻译：模拟电路合成的方法和技术。模拟电路通常包括许多电路元件，并且每个电路元件的特性和功能由许多相应的参数控制。在本发明中，所选择的关键电路组件的选择的关键设计参数以及优化目标，设计规范或/和设计约束被转换成优化计划，优化引擎通过改变电路级或系统级数值模拟来迭代所选择的关键设计参数的值被记录在优化计划中，以便找到允许模拟电路匹配设计规范/约束并且接近优化目标的优化参数和电路组件。因此，实现了模拟电路合成/设计/优化的系统自动化。

4. 发明申请

US20070153597A1 Built-in memory current test circuit 有权
标题翻译：内置内存电流测试电路
公开(公告)号：US20070153597A1
公开(公告)日：2007-07-05
申请号：US11481966
申请日：2006-07-07
申请人： Yeong-Jar Chang , Kun-Lun Luo , Jung-Chi Ho , Cheng-Wen Wu , Chin-Jung Su
发明人： Yeong-Jar Chang , Kun-Lun Luo , Jung-Chi Ho , Cheng-Wen Wu , Chin-Jung Su
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/12 , G11C29/12005 , G11C29/50 , G11C2029/5006
摘要： A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.
摘要翻译：公开了一种用于测试芯片上的存储器的内置存储器电流测试电路，其包括内置的自测电路和动态电流产生模块。内置自检电路设置在芯片上，以接收和处理测试信号，并产生控制信号以控制存储器的操作和电流控制代码。也设置在芯片上的动态电流产生模块基于当前控制码产生到存储器中的测试电流。内置存储器电流测试电路中的当前切换时间减少，因此可以执行组合功能和应力测试的集成测试。

5. 发明授权

US06950046B2 IC with built-in self-test and design method thereof 有权
标题翻译： IC内置自检及其设计方法
公开(公告)号：US06950046B2
公开(公告)日：2005-09-27
申请号：US10894054
申请日：2004-07-20
申请人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
发明人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
IPC分类号： G01R31/28 , H03M1/10 , H03M3/00
CPC分类号： H03M3/378 , H03M3/458
摘要： IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.
摘要翻译： IC内置自检及其设计方法。 IC包括SD-ADC和Dft电路。 Dft电路使用数字刺激信号来解决片上模拟测试的死锁问题，并避免热噪声。此外，根据IC的设计方法，具有不同规格的电路可以使用Dft电路，而不会对原始SD-ADC造成性能下降。

6. 发明申请

US20050174273A1 IC WITH BUILT-IN SELF-TEST AND DESIGN METHOD THEREOF 有权
标题翻译： IC内置自检及其设计方法
公开(公告)号：US20050174273A1
公开(公告)日：2005-08-11
申请号：US10894054
申请日：2004-07-20
申请人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
发明人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
IPC分类号： G01R31/28 , H03M1/10 , H03M3/00
CPC分类号： H03M3/378 , H03M3/458
摘要： IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.
摘要翻译： IC内置自检及其设计方法。 IC包括SD-ADC和Dft电路。 Dft电路使用数字刺激信号来解决片上模拟测试的死锁问题，并避免热噪声。此外，根据IC的设计方法，具有不同规格的电路可以使用Dft电路，而不会对原始SD-ADC造成性能下降。

7. 发明授权

US07319625B2 Built-in memory current test circuit 有权
标题翻译：内置内存电流测试电路
公开(公告)号：US07319625B2
公开(公告)日：2008-01-15
申请号：US11481966
申请日：2006-07-07
申请人： Yeong-Jar Chang , Kun-Lun Luo , Jung-Chi Ho , Cheng-Wen Wu , Chin-Jung Su
发明人： Yeong-Jar Chang , Kun-Lun Luo , Jung-Chi Ho , Cheng-Wen Wu , Chin-Jung Su
IPC分类号： G11C7/00
CPC分类号： G11C29/12 , G11C29/12005 , G11C29/50 , G11C2029/5006
摘要： A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.
摘要翻译：公开了一种用于测试芯片上的存储器的内置存储器电流测试电路，其包括内置的自测电路和动态电流产生模块。内置自检电路设置在芯片上，以接收和处理测试信号，并产生控制信号以控制存储器的操作和电流控制代码。也设置在芯片上的动态电流产生模块基于当前控制码产生到存储器中的测试电流。内置存储器电流测试电路中的当前切换时间减少，因此可以执行组合功能和应力测试的集成测试。

8. 发明申请

US20100283507A1 CURRENT SOURCE APPLICABLE TO A CONTROLLABLE DELAY LINE AND DESIGN METHOD THEREOF 有权
标题翻译：适用于可控延时线的电流源及其设计方法
公开(公告)号：US20100283507A1
公开(公告)日：2010-11-11
申请号：US12436988
申请日：2009-05-07
申请人： Chi-Che Chen , Jung-Chi Ho
发明人： Chi-Che Chen , Jung-Chi Ho
IPC分类号： H03K19/094 , H03K19/0175 , H03H11/26
CPC分类号： H03M1/82 , H03K5/133 , H03K2005/00065
摘要： A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with thermometer code current sources do.
摘要翻译：提供了电流源和设计电流源的方法。电流源通过递归规则设计，并使可控延迟线提供线性延迟，并占用比具有温度计代码电流源的常规可控延迟线更小的面积。

9. 发明申请

US20070244686A1 Calibration method for mixed-mode simulation 审中-公开
标题翻译：混合模式模拟的校准方法
公开(公告)号：US20070244686A1
公开(公告)日：2007-10-18
申请号：US11481846
申请日：2006-07-07
申请人： Yaong-Jar Chang , Yung-Chieh Lin , Jung-Chi Ho , Pei-Wen Luo
发明人： Yaong-Jar Chang , Yung-Chieh Lin , Jung-Chi Ho , Pei-Wen Luo
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A calibration method of a mixed mode simulation calibrates standard delay times in a standard delay format and includes obtaining a digital output circuit from a digital circuit, obtaining an analog output circuit from an analog circuit, performing a simulation on the digital output circuit connected to the analog output circuit to obtain an ideal output, obtaining a first delay time according to the standard delay times of the digital output circuit, performing a calibrative analog-to-digital mixed mode simulation using the first delay time to obtain an analog-to-digital mixed output, comparing the ideal output and the analog-to-digital mixed output to calibrate the first delay time, and calibrating the standard delay times of the digital output circuit according to the calibrated first delay time.
摘要翻译：混合模式模拟的校准方法以标准延迟格式校准标准延迟时间，并且包括从数字电路获得数字输出电路，从模拟电路获得模拟输出电路，对连接到模拟电路的数字输出电路执行仿真模拟输出电路以获得理想输出，根据数字输出电路的标准延迟时间获得第一延迟时间，使用第一延迟时间执行校准模数混合模式仿真，以获得模数转换混合输出，比较理想输出和模数混合输出以校准第一延迟时间，并根据校准的第一延迟时间校准数字输出电路的标准延迟时间。

10. 发明申请

US20150271914A1 INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路
公开(公告)号：US20150271914A1
公开(公告)日：2015-09-24
申请号：US14274784
申请日：2014-05-12
申请人： Ying-Jiunn Lai , Jung-Chi Ho
发明人： Ying-Jiunn Lai , Jung-Chi Ho
IPC分类号： H05K1/02 , H05K1/11
CPC分类号： H01L23/58 , H01L23/50 , H01L23/5227 , H01L23/645 , H01L23/647 , H01L23/66 , H01L2223/6611 , H01L2223/6638 , H01L2224/05554 , H01L2224/48091 , H01L2224/49175 , H04L25/00 , H01L2924/00014
摘要： An integrated circuit (IC) is provided. The IC includes a chip/die and a package. The chip/die includes a first bonding pad, a second bonding pad, a core circuit and a resistance unit. The first bonding pad is coupled to a signal path of the core circuit. The two ends of the resistance unit are respectively coupled to the first bonding pad and the second bonding pad. The package includes a pin and a low-pass circuit. The pin is electrically connected to the first bonding pad. The low-pass circuit is electrically connected to the second bonding pad.
摘要翻译：提供集成电路（IC）。 IC包括芯片/管芯和封装。芯片/裸片包括第一焊盘，第二焊盘，芯电路和电阻单元。第一焊盘耦合到核心电路的信号路径。电阻单元的两端分别耦合到第一焊盘和第二接合焊盘。封装包括一个引脚和一个低通电路。引脚电连接到第一焊盘。低通电路电连接到第二接合焊盘。

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