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1. 发明授权

US10192968B2 Semiconductor devices having gate structures with skirt regions 有权
公开(公告)号：US10192968B2
公开(公告)日：2019-01-29
申请号：US14988819
申请日：2016-01-06
申请人： Jung-Gun You , Myung-Yoon Um , Young-Joon Park , Jeong-Hyo Lee , Ji-Yong Ha , Jun-Sun Hwang
发明人： Jung-Gun You , Myung-Yoon Um , Young-Joon Park , Jeong-Hyo Lee , Ji-Yong Ha , Jun-Sun Hwang
IPC分类号： H01L29/423 , H01L29/78 , H01L21/28 , H01L29/40 , H01L29/66 , H01L21/762 , H01L21/8234 , H01L29/49
摘要： Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.

2. 发明申请

US20160204264A1 SEMICONDUCTOR DEVICES HAVING GATE STRUCTURES WITH SKIRT REGIONS 审中-公开
标题翻译：具有裙带结构的半导体器件
公开(公告)号：US20160204264A1
公开(公告)日：2016-07-14
申请号：US14988819
申请日：2016-01-06
申请人： Jung-Gun You , Myung-Yoon Um , Young-Joon Park , Jeong-Hyo Lee , Ji-Yong Ha , Jun-Sun Hwang
发明人： Jung-Gun You , Myung-Yoon Um , Young-Joon Park , Jeong-Hyo Lee , Ji-Yong Ha , Jun-Sun Hwang
IPC分类号： H01L29/78 , H01L29/423
CPC分类号： H01L29/42376 , H01L21/28088 , H01L21/28114 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L29/401 , H01L29/4238 , H01L29/4966 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/7851 , H01L29/7853
摘要： Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.
摘要翻译：提供一种半导体器件及其制造方法。半导体器件包括从基板向上突出并沿第一方向延伸的有源鳍片和栅极结构，该栅极结构沿与第一方向交叉的第二方向延伸以跨越有源鳍片，其中栅极结构的下部的第一宽度接触有源翅片大于栅极结构的与有源鳍片间隔开的下部的第二宽度。

3. 发明授权

US10074726B2 Fin semiconductor device including dummy gate on isolation layer 有权
公开(公告)号：US10074726B2
公开(公告)日：2018-09-11
申请号：US14710776
申请日：2015-05-13
申请人： Jung-Gun You , Young-Joon Park , Ji-Yong Ha
发明人： Jung-Gun You , Young-Joon Park , Ji-Yong Ha
IPC分类号： H01L27/088 , H01L29/423 , H01L29/78 , H01L29/06 , H01L29/49 , H01L29/51 , H01L27/02 , H01L21/8234
CPC分类号： H01L29/42376 , H01L21/823431 , H01L21/823437 , H01L21/823456 , H01L21/823821 , H01L27/0207 , H01L27/0886 , H01L29/0649 , H01L29/4916 , H01L29/518 , H01L29/7851
摘要： A semiconductor device and a method of manufacturing a semiconductor device, the device including an active fin protruding from a substrate and extending in a first direction, a first device isolation region disposed at a sidewall of the active fin and extending in a second direction, the second direction crossing the first direction, a normal gate electrode crossing the active fin, a first dummy gate electrode having an undercut portion on the first device isolation region, the first dummy gate electrode extending in the second direction, and a first filler filling the undercut portion on the first device isolation region, wherein the undercut portion is disposed at a lower portion of the first dummy gate electrode.

4. 发明申请

US20160163699A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160163699A1
公开(公告)日：2016-06-09
申请号：US14824896
申请日：2015-08-12
申请人： Jung-Gun You , Jeong-Hyo Lee
发明人： Jung-Gun You , Jeong-Hyo Lee
IPC分类号： H01L27/088 , H01L29/49 , H01L29/06
CPC分类号： H01L21/823431 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L27/0207 , H01L27/0886 , H01L29/0649 , H01L29/495 , H01L29/4966
摘要： A semiconductor device is provided as follows. Active fins protrude from a substrate, extending in a first direction. A first device isolation layer is disposed at a first side of the active fins. A second device isolation layer is disposed at a second side of the active fins. A top surface of the second device isolation layer is higher than a top surface of the first device isolation layer and the second side is opposite to the first side. A normal gate extends across the active fins in a second direction crossing the first direction. A first dummy gate extends across the active fins and the first device isolation layer in the second direction. A second dummy gate extends across the second device isolation layer in the second direction.
摘要翻译：如下提供半导体器件。活性翅片从基底突出，沿第一方向延伸。第一器件隔离层设置在活性鳍片的第一侧。第二器件隔离层设置在活性鳍片的第二侧。第二器件隔离层的顶表面高于第一器件隔离层的顶表面，而第二侧与第一侧相反。正常门在与第一方向交叉的第二方向上延伸穿过活动散热片。第一伪栅极沿着第二方向跨过活性鳍片和第一器件隔离层延伸。第二伪栅极在第二方向上跨越第二器件隔离层延伸。

5. 发明授权

US09601628B2 Semiconductor device having asymmetric fin-shaped pattern 有权
公开(公告)号：US09601628B2
公开(公告)日：2017-03-21
申请号：US14983904
申请日：2015-12-30
申请人： Jung-Gun You , Se-Wan Park , Baik-Min Sung , Bo-Cheol Jeong
发明人： Jung-Gun You , Se-Wan Park , Baik-Min Sung , Bo-Cheol Jeong
IPC分类号： H01L29/06 , H01L29/78 , H01L27/088 , H01L21/762 , H01L21/311
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823481 , H01L29/0649 , H01L29/7851 , H01L29/7853 , H01L29/7854
摘要： Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.

6. 发明授权

US09620406B2 Methods for fabricating semiconductor devices having fin-shaped patterns by selectively removing oxidized fin-shaped patterns 有权
公开(公告)号：US09620406B2
公开(公告)日：2017-04-11
申请号：US14968999
申请日：2015-12-15
申请人： Jung-Gun You , Se-Wan Park , Seung-Woo Do , In-Won Park , Sug-Hyun Sung
发明人： Jung-Gun You , Se-Wan Park , Seung-Woo Do , In-Won Park , Sug-Hyun Sung
IPC分类号： H01L21/762 , H01L29/66 , H01L29/417 , H01L29/78 , H01L29/165
CPC分类号： H01L29/66545 , H01L21/30604 , H01L21/3085 , H01L21/76224 , H01L29/165 , H01L29/41766 , H01L29/66795 , H01L29/6681 , H01L29/66818 , H01L29/7848 , H01L29/785
摘要： A method for fabricating a semiconductor device is provided. The method includes forming a first fin-shaped pattern including an upper part and a lower part on a substrate, forming a second fin-shaped pattern by removing a part of the upper part of the first fin-shaped pattern, forming a dummy gate electrode intersecting with the second fin-shaped pattern on the second fin-shaped pattern, and forming a third fin-shaped pattern by removing a part of an upper part of the second fin-shaped pattern after forming the dummy gate electrode, wherein a width of the upper part of the second fin-shaped pattern is smaller than a width of the upper part of the first fin-shaped pattern and is greater than a width of an upper portion of the third fin-shaped pattern.

7. 发明申请

US20160293599A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160293599A1
公开(公告)日：2016-10-06
申请号：US14995457
申请日：2016-01-14
申请人： Jung-Gun You , Hyung-Jong Lee , Sung-Min Kim , Chong-Kwang Chang
发明人： Jung-Gun You , Hyung-Jong Lee , Sung-Min Kim , Chong-Kwang Chang
IPC分类号： H01L27/088 , H01L29/06 , H01L23/528
CPC分类号： H01L27/0886 , H01L23/485 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L29/0649
摘要： A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.
摘要翻译：一种半导体器件，包括由第一沟槽分隔的第一和第二鳍状图案; 与第一和第二鳍状图案相交的栅电极; 以及在所述栅极电极的至少一侧上的触点，所述触点接触所述第一鳍状图案，所述触点具有不接触所述第二鳍状图案的底表面，从所述第一沟槽的底部到最顶端的高度在第一鳍状物的第一鳍状物与第一鳍状物的第一高度相交的区域中的第一鳍状图案和从第一沟槽的底部到第二鳍状图案的最上端的高度，沿着栅极延伸的方向延伸的接触部将第二翅片图案与第二高度相交，第一高度小于第二高度。

8. 发明申请

US20160211379A1 SEMICONDUCTOR DEVICE HAVING ASYMMETRIC FIN-SHAPED PATTERN 有权
标题翻译：具有不对称精细形状图案的半导体器件
公开(公告)号：US20160211379A1
公开(公告)日：2016-07-21
申请号：US14983904
申请日：2015-12-30
申请人： Jung-Gun You , Se-Wan Park , Baik-Min Sung , Bo-Cheol Jeong
发明人： Jung-Gun You , Se-Wan Park , Baik-Min Sung , Bo-Cheol Jeong
IPC分类号： H01L29/78 , H01L29/06 , H01L27/088
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823481 , H01L29/0649 , H01L29/7851 , H01L29/7853 , H01L29/7854
摘要： Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.
摘要翻译：提供半导体器件，其包括具有彼此面对的第一和第二侧壁的第一鳍状图案和与第一鳍状图案的至少一部分接触的场绝缘膜。第一鳍状图案包括与场绝缘膜接触的第一鳍状图案的下部; 所述第一鳍状图案的上部不与所述场绝缘膜接触; 第一鳍状图案的下部与第一鳍状图案的上部之间的第一边界; 以及垂直于第一边界并且满足第一鳍状图案的上部的顶部的第一鳍中心线。第一鳍状图案的上部的第一侧壁和第一鳍状图案的上部的第二侧壁相对于第一翅片中心线是不对称的。

9. 发明申请

US20180006032A1 Semiconductor Devices and Fabricating Methods Thereof 审中-公开
公开(公告)号：US20180006032A1
公开(公告)日：2018-01-04
申请号：US15708512
申请日：2017-09-19
申请人： Jung-Gun You , Sug-Hyun Sung
发明人： Jung-Gun You , Sug-Hyun Sung
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/06
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823481 , H01L29/0649 , H01L29/0657 , H01L29/7854
摘要： Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.

10. 发明申请

US20160218180A1 METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING FIN-SHAPED PATTERNS 有权
标题翻译：用于制造具有精细形状图案的半导体器件的方法
公开(公告)号：US20160218180A1
公开(公告)日：2016-07-28
申请号：US14968999
申请日：2015-12-15
申请人： Jung-Gun You , Se-Wan PARK , Seung-Woo DO , In-Won PARK , Sug-Hyun SUNG
发明人： Jung-Gun You , Se-Wan PARK , Seung-Woo DO , In-Won PARK , Sug-Hyun SUNG
IPC分类号： H01L29/10 , H01L29/417 , H01L21/762 , H01L29/66
CPC分类号： H01L29/66545 , H01L21/30604 , H01L21/3085 , H01L21/76224 , H01L29/165 , H01L29/41766 , H01L29/66795 , H01L29/6681 , H01L29/66818 , H01L29/7848 , H01L29/785
摘要： A method for fabricating a semiconductor device is provided. The method includes forming a first fin-shaped pattern including an upper part and a lower part on a substrate, forming a second fin-shaped pattern by removing a part of the upper part of the first fin-shaped pattern, forming a dummy gate electrode intersecting with the second fin-shaped pattern on the second fin-shaped pattern, and forming a third fin-shaped pattern by removing a part of an upper part of the second fin-shaped pattern after forming the dummy gate electrode, wherein a width of the upper part of the second fin-shaped pattern is smaller than a width of the upper part of the first fin-shaped pattern and is greater than a width of an upper portion of the third fin-shaped pattern.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在衬底上形成包括上部和下部的第一鳍状图案，通过去除第一鳍状图案的上部的一部分形成第二鳍状图案，形成虚拟栅电极与第二鳍状图案上的第二鳍状图案相交，并且在形成虚拟栅电极之后，通过去除第二鳍状图案的上部的一部分来形成第三鳍状图案，其中宽度第二鳍状图案的上部小于第一鳍状图案的上部的宽度，并且大于第三鳍状图案的上部的宽度。

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