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1. 发明申请

US20140231740A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20140231740A1
公开(公告)日：2014-08-21
申请号：US13904337
申请日：2013-05-29
申请人： Kabushiki Kaisha Toshiba
发明人： Ryuji Ohba
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , H01L27/2418 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148
摘要： According to one embodiment, a memory device includes first and second conductive layers, a variable resistance portion, and a multiple tunnel junction portion. The variable resistance portion is provided between the first and second conductive layers. The multiple tunnel junction portion is provided between the first conductive layer and the variable resistance portion, and includes first, second, and third tunnel insulating films, and first and second nanocrystal layers. The first nanocrystal layer between the first and second tunnel insulating films includes first conductive minute particles. The second nanocrystal layer between the second and third tunnel insulating films includes second conductive minute particles.
摘要翻译：根据一个实施例，存储器件包括第一和第二导电层，可变电阻部分和多个隧道结部分。可变电阻部分设置在第一和第二导电层之间。多重隧道结部分设置在第一导电层和可变电阻部分之间，并且包括第一，第二和第三隧道绝缘膜以及第一和第二纳米晶体层。第一和第二隧道绝缘膜之间的第一纳米晶层包括第一导电微小颗粒。第二和第三隧道绝缘膜之间的第二纳米晶层包括第二导电微小颗粒。

2. 发明授权

US09041091B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09041091B2
公开(公告)日：2015-05-26
申请号：US13957802
申请日：2013-08-02
申请人： Kabushiki Kaisha Toshiba
发明人： Ryuji Ohba
IPC分类号： H01L29/788 , H01L21/336 , H01L29/792 , H01L21/28 , H01L29/423 , H01L29/66 , H01L27/115
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： According to one embodiment, a device includes a fin type active area on a semiconductor substrate, the active area having an upper surface with a taper shape, having a width in a first direction, and extending in a second direction intersect with the first direction, a first insulating layer on the active area, a charge storage layer on the first insulating layer, the charge storage layer having an upper surface with a taper shape, a second insulating layer covering the upper surface of the charge storage layer, and a control gate electrode on the second insulating layer, the control gate electrode extending in the first direction.
摘要翻译：根据一个实施例，一种器件包括在半导体衬底上的翅片型有源区，该有源区具有锥形形状的上表面，具有在第一方向上的宽度，并且在第二方向上与第一方向相交，所述有源区上的第一绝缘层，所述第一绝缘层上的电荷存储层，所述电荷存储层具有锥形形状的上表面，覆盖所述电荷存储层的上表面的第二绝缘层，以及控制栅极电极在第二绝缘层上，控制栅电极沿第一方向延伸。

3. 发明授权

US08969843B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08969843B2
公开(公告)日：2015-03-03
申请号：US13904337
申请日：2013-05-29
申请人： Kabushiki Kaisha Toshiba
发明人： Ryuji Ohba
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , H01L27/2418 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148
摘要： According to one embodiment, a memory device includes first and second conductive layers, a variable resistance portion, and a multiple tunnel junction portion. The variable resistance portion is provided between the first and second conductive layers. The multiple tunnel junction portion is provided between the first conductive layer and the variable resistance portion, and includes first, second, and third tunnel insulating films, and first and second nanocrystal layers. The first nanocrystal layer between the first and second tunnel insulating films includes first conductive minute particles. The second nanocrystal layer between the second and third tunnel insulating films includes second conductive minute particles.
摘要翻译：根据一个实施例，存储器件包括第一和第二导电层，可变电阻部分和多个隧道结部分。可变电阻部分设置在第一和第二导电层之间。多重隧道结部分设置在第一导电层和可变电阻部分之间，并且包括第一，第二和第三隧道绝缘膜以及第一和第二纳米晶体层。第一和第二隧道绝缘膜之间的第一纳米晶层包括第一导电微小颗粒。第二和第三隧道绝缘膜之间的第二纳米晶层包括第二导电微小颗粒。

4. 发明授权

US09721654B1 Memory device 有权
公开(公告)号：US09721654B1
公开(公告)日：2017-08-01
申请号：US15267925
申请日：2016-09-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ryuji Ohba
IPC分类号： G11C11/00 , G11C13/00 , H01L45/00
CPC分类号： G11C13/0007 , G11C13/0002 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2213/11 , G11C2213/15 , G11C2213/32 , G11C2213/54 , G11C2213/77 , H01L45/08 , H01L45/1246 , H01L45/1266 , H01L45/146
摘要： A memory device according to one embodiment includes a first interconnection, a second interconnection, a charge storage portion provided between the first interconnection and the second interconnection, a tunnel film provided between the first interconnection and the charge storage portion, and a block film. the charge storage portion is capable of accumulating an electron. The tunnel film includes a fine particulate layer that including conductive fine particulates satisfying the Coulomb blockade condition, a first tunnel insulating layer provided between the first interconnection and the fine particulate layer, and a second tunnel insulating layer provided between the fine particulate layer and the charge storage portion. The block film is provided between the charge storage portion and the second interconnection. The block film has an energy structure in which no concave portion with an energy barrier lower than energy barriers on both sides thereof is present.

5. 发明申请

US20150263121A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150263121A1
公开(公告)日：2015-09-17
申请号：US14483601
申请日：2014-09-11
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kana HIRAYAMA , Ryuji Ohba , Takeshi Kamigaichi
IPC分类号： H01L29/51 , H01L29/423 , H01L21/28 , H01L29/66 , H01L21/762 , H01L27/115 , H01L29/788 , H01L29/49
CPC分类号： H01L27/11519 , H01L21/76224 , H01L27/11521 , H01L29/40114 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A semiconductor device including semiconductor substrate having an active region and an element isolation region, the active region isolated by the element isolation region, the element isolation region provided with an element isolation trench; a memory-cell transistor formed above the semiconductor substrate and having a gate electrode formed above the active region via a first insulating film, the gate electrode formed of a stack including a floating gate electrode, a first interelectrode insulating film, and a control gate electrode; an element isolation insulating film filled in the element isolation trench; and a second interelectrode insulating film disposed above the element isolation insulating film so as to form a stack of the second interelectrode insulating film and the control electrode above the element isolation insulating and a dielectric constant of the second interelectrode insulating film being higher than a dielectric constant of the first interelectrode insulating film.
摘要翻译：一种半导体器件，包括具有有源区和元件隔离区的半导体衬底，所述有源区由元件隔离区隔离，元件隔离区设置有元件隔离沟槽; 形成在所述半导体衬底上并且具有通过第一绝缘膜形成在所述有源区上方的栅电极的存储单元晶体管，所述栅电极由包括浮置栅电极，第一电极间绝缘膜和控制栅电极 ; 填充在元件隔离沟槽中的元件隔离绝缘膜; 以及第二电极间绝缘膜，其设置在所述元件隔离绝缘膜的上方，以在所述元件隔离绝缘件的上方形成所述第二电极间绝缘膜和所述控制电极的叠层，并且所述第二电极间绝缘膜的介电常数高于介电常数的第一电极间绝缘膜。

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