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1. 发明授权

US09224850B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09224850B2
公开(公告)日：2015-12-29
申请号：US13957330
申请日：2013-08-01
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masakazu Goto , Shigeru Kawanaka , Akira Hokazono , Tatsuya Ohguro , Yoshiyuki Kondo
IPC分类号： H01L29/66 , H01L29/78 , H01L29/739 , H01L21/8234
CPC分类号： H01L29/78 , H01L21/823418 , H01L21/823493 , H01L29/66356 , H01L29/66477 , H01L29/7391
摘要： In one embodiment, a first main terminal region of a first conductivity type and a second main terminal region of a second conductivity type, which is an opposite conductivity type of the first conductivity type, formed in the semiconductor substrate so as to sandwich a gate electrode, a diffusion layer of the second conductivity type coming in contact with the first and second element isolation insulator films and having an upper surface in a position deeper than lower surfaces of the first and second main terminal regions, a first well region of the first conductivity type formed between the first main terminal region and the diffusion layer, and a second well region of the first conductivity type formed between the second main terminal region and the diffusion layer. The second well region has a impurity concentration higher than that of the first well region.
摘要翻译：在一个实施例中，在半导体衬底中形成第一导电类型的第一主端子区域和第二导电类型的与第一导电类型相反的导电类型的第二主端子区域，以夹持栅电极第二导电类型的扩散层与第一和第二元件隔离绝缘膜接触并且具有比第一和第二主端子区域的下表面更深的位置的上表面，第一导电性的第一阱区域形成在第一主端子区域和扩散层之间的第一阱区域，以及形成在第二主端子区域和扩散层之间的第一导电类型的第二阱区域。第二阱区域的杂质浓度高于第一阱区域。

2. 发明授权

US09048267B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09048267B2
公开(公告)日：2015-06-02
申请号：US14145141
申请日：2013-12-31
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiyuki Kondo , Masakazu Goto , Shigeru Kawanaka , Toshitaka Miyata
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66977 , H01L29/165 , H01L29/66356 , H01L29/66659 , H01L29/7391 , H01L29/7833
摘要： A semiconductor device according to the present embodiment includes a semiconductor layer. A gate dielectric film is provided on a surface of the semiconductor layer. A gate electrode is provided on the semiconductor layer via the gate dielectric film. A drain layer of a first conductivity type is provided in a part of the semiconductor layer on a side of a first end of the gate electrode. A source layer of a second conductivity type is provided in a part of the semiconductor layer on a side of a second end of the gate electrode and below the gate electrode. The source layer has a substantially uniform impurity concentration at the part of the semiconductor layer below the gate electrode. Voltages of a same polarity are applied to the gate electrode and the drain layer.
摘要翻译：根据本实施例的半导体器件包括半导体层。在半导体层的表面上设置栅极电介质膜。栅电极经由栅极电介质膜设置在半导体层上。第一导电类型的漏极层设置在栅电极的第一端侧的半导体层的一部分中。第二导电类型的源极层设置在半导体层的位于栅电极的第二端的一侧并且位于栅电极下方的一部分。源极层在栅电极下方的半导体层的部分具有基本均匀的杂质浓度。对栅电极和漏极层施加相同极性的电压。

3. 发明授权

US09082640B2 Pass gate and semiconductor storage device having the same 有权
标题翻译：通过栅极和具有相同的半导体存储器件
公开(公告)号：US09082640B2
公开(公告)日：2015-07-14
申请号：US13779358
申请日：2013-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Keisuke Nakatsuka , Shigeru Kawanaka
IPC分类号： H01L27/088 , H01L27/11 , H01L27/02 , G11C11/412 , H01L29/739
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0207 , H01L27/1104 , H01L29/7391
摘要： According to an embodiment, a semiconductor storage device includes an SRAM cell. The SRAM cell includes first and second transfer gates each comprising a pass gate. The pass gate includes first and second tunnel transistors. The first tunnel transistor includes a first conductivity type first diffusion region as a source or drain region, a second conductivity type second diffusion region as a drain or source region, and a gate electrode supplied with a control voltage. The second tunnel transistor includes a first conductivity type first diffusion region as a source or drain region, a second conductivity type second diffusion region as a drain or source region electrically connected to the second diffusion region of the first tunnel transistor, and a gate electrode electrically connected to the gate electrode of the first tunnel transistor.
摘要翻译：根据实施例，半导体存储装置包括SRAM单元。 SRAM单元包括每个包括通孔的第一和第二传输门。通路包括第一和第二隧道晶体管。第一隧道晶体管包括作为源极或漏极区域的第一导电类型的第一扩散区域，作为漏极或源极区域的第二导电类型的第二扩散区域和被提供有控制电压的栅电极。第二隧道晶体管包括作为源极或漏极区域的第一导电类型的第一扩散区域，与第一隧道晶体管的第二扩散区域电连接的漏极或源极区域的第二导电类型的第二扩散区域，以及电极连接到第一隧道晶体管的栅电极。

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