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1. 发明申请

US20140085988A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20140085988A1
公开(公告)日：2014-03-27
申请号：US14088744
申请日：2013-11-25
申请人： Kabushiki Kaisha Toshiba
发明人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3427 , G11C16/349
摘要： A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
摘要翻译：根据本发明的一个实施例的非易失性半导体存储器件包括：存储单元阵列和控制电路。控制电路执行第一读取操作和第二读取操作。第一读取操作是通过将控制栅电极和所选择的存储单元的源之间的电压设置为第一值来读取设置在所选存储单元中的阈值电压的操作。第二读取操作是通过将控制栅电极和所选择的存储单元的源之间的电压设置为低于第一值的第二值来读取设置在所选存储单元中的阈值电压的操作。当执行第二读取操作时，控制电路将所选存储单元的控制栅电极的电压保持为0或正值。

2. 发明申请

US20140050027A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20140050027A1
公开(公告)日：2014-02-20
申请号：US14066875
申请日：2013-10-30
申请人： Kabushiki Kaisha Toshiba
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

3. 发明授权

US09530510B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US09530510B2
公开(公告)日：2016-12-27
申请号：US14945569
申请日：2015-11-19
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C16/04 , G11C16/14 , G11C11/56 , G11C16/16 , G11C16/34 , G11C16/10
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

4. 发明授权

US09508442B2 Non-volatile semiconductor storage device 有权
公开(公告)号：US09508442B2
公开(公告)日：2016-11-29
申请号：US14990609
申请日：2016-01-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yasuhiro Shiino , Daisuke Kouno , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi
IPC分类号： G11C11/34 , G11C16/14 , G11C16/16 , G11C16/34
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.

5. 发明申请

US20160118127A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
公开(公告)号：US20160118127A1
公开(公告)日：2016-04-28
申请号：US14990609
申请日：2016-01-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yasuhiro Shiino , Daisuke Kouno , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi
IPC分类号： G11C16/14 , G11C16/34
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.

6. 发明授权

US09047958B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US09047958B2
公开(公告)日：2015-06-02
申请号：US13707851
申请日：2012-12-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yasuhiro Shiino , Shigefumi Irieda
IPC分类号： G11C11/34 , G11C16/10 , G11C11/56 , G11C16/34
摘要： A non-volatile semiconductor memory device according to one embodiment includes: a cell array; and a data writing unit that repeatedly executes a write loop including a programming operation of applying a program voltage to a selected word line and a passage voltage to non-selected word lines during writing of data, in which, when a difference between the passage voltage used in an n-th write loop and the passage voltage used in an n+1-th write loop is expressed as ΔVn and when a condition of L

7. 发明授权

US08787091B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08787091B2
公开(公告)日：2014-07-22
申请号：US14066875
申请日：2013-10-30
申请人： Kabushiki Kaisha Toshiba
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
摘要翻译：非易失性半导体存储器件包括：控制电路，被配置为控制将非易失性存储器单元设置为非易失性存储单元的第一阈值电压分布状态的软编程操作。当非易失性存储单元的特性处于第一状态时，控制电路通过将用于将非易失性存储单元设置为第一阈值电压分布状态的第一电压施加到第一字线来执行软编程操作，并且施加第二电压高于第一个电压到第二个字线。当非易失性存储单元的特性处于第二状态时，控制电路通过向第一字线施加等于或低于第一电压的第三电压并施加低于第二电压的第四电压来执行软编程操作到第二个字线。

8. 发明申请

US20130135939A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130135939A1
公开(公告)日：2013-05-30
申请号：US13749029
申请日：2013-01-24
申请人： Kabushiki Kaisha Toshiba
发明人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3427 , G11C16/349
摘要： A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

9. 发明授权

US09672926B2 Apparatus and method of programming and verification for a nonvolatile semiconductor memory device 有权
公开(公告)号：US09672926B2
公开(公告)日：2017-06-06
申请号：US14014125
申请日：2013-08-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yasuhiro Shiino , Nobushi Matsuura , Masashi Yoshida , Eietsu Takahashi
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3459 , G11C2211/5621
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to repeat a program operation and a verify operation. The control circuit performs a first verify operation of sensing whether threshold voltages of selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage (first threshold voltage

10. 发明授权

US09472295B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US09472295B2
公开(公告)日：2016-10-18
申请号：US14677111
申请日：2015-04-02
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
IPC分类号： G11C16/04 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3427 , G11C16/349
摘要： A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

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