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1. 发明授权

US09848504B2 Electronic device having a housing for suppression of electromagnetic noise 有权
公开(公告)号：US09848504B2
公开(公告)日：2017-12-19
申请号：US14722310
申请日：2015-05-27
申请人： Kabushiki Kaisha Toshiba
发明人： Tadahiro Sasaki , Hiroshi Yamada
IPC分类号： H05K5/02 , H05K9/00 , H01P1/20
CPC分类号： H05K5/0239 , H01P1/2005 , H05K9/0056 , H05K9/0081
摘要： According to an embodiment, an electronic device includes a housing, metal patches, and a first metal member. The housing includes a bottom, a lid, and a side unit. The side unit is disposed to enclose a space between the bottom and the lid. A circuit substrate is disposed on a bottom surface of the bottom. The side unit is conductive and connected to a ground potential. The metal patches are disposed on a lid surface of the lid. The metal patches are arranged periodically in a first direction and a second direction. The second direction intersects the first direction. The metal patches are connected to the ground potential. The first metal member is disposed on the lid surface. The first metal member is connected to the ground potential. The first metal member includes a first portion. The first portion contacts a first surface of the side unit.

2. 发明申请

US20150021748A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20150021748A1
公开(公告)日：2015-01-22
申请号：US14332542
申请日：2014-07-16
申请人： Kabushiki Kaisha Toshiba
发明人： Tadahiro SASAKI , Kazuhiko Itaya , Hiroshi Yamada , Yutaka Onozuka , Nobuto Managaki
IPC分类号： H01L23/66 , H01L23/053
CPC分类号： H01L23/66 , H01L23/053 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device of an embodiment includes: a substrate, a high-frequency integrated circuit being provided on the substrate, a cap, and a sealing wall provided between the substrate and the cap. The cap includes a first conductive layer, a second conductive layer, an insulating layer provided between the first conductive layer and the second conductive layer, and a conductive via provided in the insulating layer. The conductive via connects the first conductive layer and the second conductive layer. The first conductive layer or the second conductive layer is connected to a ground potential. The sealing wall surrounds the high-frequency integrated circuit.
摘要翻译：实施例的半导体器件包括：基板，设置在基板上的高频集成电路，盖和设置在基板和盖之间的密封壁。盖包括第一导电层，第二导电层，设置在第一导电层和第二导电层之间的绝缘层，以及设置在绝缘层中的导电通孔。导电通孔连接第一导电层和第二导电层。第一导电层或第二导电层连接到接地电位。密封壁围绕高频集成电路。

3. 发明申请

US20130234308A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20130234308A1
公开(公告)日：2013-09-12
申请号：US13766195
申请日：2013-02-13
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroshi Yamada , Yutaka Onozuka , Atsuko Iida , Kazuhiko Itaya
IPC分类号： H01L21/78 , H01L21/56 , H01L23/495
CPC分类号： H01L25/105 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/76802 , H01L21/78 , H01L23/3114 , H01L23/3135 , H01L23/481 , H01L23/495 , H01L23/49572 , H01L23/49838 , H01L23/5226 , H01L24/14 , H01L24/24 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/16 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/13023 , H01L2224/13024 , H01L2224/24137 , H01L2224/24195 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73267 , H01L2224/97 , H01L2225/1035 , H01L2225/1064 , H01L2924/181 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2224/85 , H01L2924/00012
摘要： A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.

4. 发明申请

US20170148713A1 CONNECTION MEMBER, SEMICONDUCTOR DEVICE, AND STACKED STRUCTURE 审中-公开
公开(公告)号：US20170148713A1
公开(公告)日：2017-05-25
申请号：US15369443
申请日：2016-12-05
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Atsuko IIDA , Tadahiro Sasaki , Nobuto Managaki , Yutaka Onozuka , Hiroshi Yamada
IPC分类号： H01L23/498 , H01L23/66 , H01L25/065
CPC分类号： H01L23/49827 , H01L23/04 , H01L23/49822 , H01L23/5389 , H01L23/60 , H01L23/66 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/95 , H01L24/96 , H01L25/0657 , H01L2223/6616 , H01L2223/6627 , H01L2223/6677 , H01L2223/6683 , H01L2224/02311 , H01L2224/02371 , H01L2224/02381 , H01L2224/0239 , H01L2224/0345 , H01L2224/0401 , H01L2224/04105 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/12105 , H01L2224/16225 , H01L2224/2101 , H01L2224/2105 , H01L2224/211 , H01L2224/214 , H01L2224/24195 , H01L2224/82106 , H01L2224/95 , H01L2224/96 , H01L2225/0652 , H01L2225/06548 , H01L2924/15788 , H01L2924/19105 , H01P1/20 , H01P1/2005 , H01P1/202 , H01P5/028 , H05K1/117 , H05K3/403 , H05K2201/0919 , H01L2924/00 , H01L2224/19 , H01L2224/03 , H01L2924/00014 , H01L2224/0231 , H01L2924/01013 , H01L2924/01029 , H01L2924/01079
摘要： A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.

5. 发明授权

US09607949B2 Semiconductor device having semiconductor chips in resin and electronic circuit device with the semiconductor device 有权
公开(公告)号：US09607949B2
公开(公告)日：2017-03-28
申请号：US14641864
申请日：2015-03-09
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroshi Yamada
IPC分类号： H01L25/065 , H01L23/538 , H01L23/31 , H01L23/04 , H01L23/00 , H01L23/29 , H01L23/433 , H01L23/36 , H01L23/498 , H01L21/56
CPC分类号： H01L23/5386 , H01L21/568 , H01L23/295 , H01L23/36 , H01L23/4334 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L25/0652 , H01L2224/0401 , H01L2224/04105 , H01L2224/05568 , H01L2224/0558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/12105 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13184 , H01L2224/1403 , H01L2224/14135 , H01L2224/16225 , H01L2224/24137 , H01L2224/24195 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2924/01029 , H01L2924/01047 , H01L2924/1424 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/0105 , H01L2924/00 , H01L2224/11
摘要： A semiconductor device includes a first semiconductor unit including a plurality of first semiconductor chips, an organic resin provided between the first semiconductor chips, a wiring layer provided above the first semiconductor chips to electrically connect the first semiconductor chips to each other, and a plurality of connecting terminals provided on an upper portion of the wiring layer and a second semiconductor unit fixed to a wiring layer side of the first semiconductor unit, the second semiconductor unit fixed to a region sandwiched between the connecting terminals, the second semiconductor unit having a second semiconductor chip, the second semiconductor unit electrically connected to the first semiconductor unit.

6. 发明授权

US09397057B2 Plurality of semiconductor devices in resin with a via 有权
标题翻译：具有通孔的树脂中的多种半导体器件
公开(公告)号：US09397057B2
公开(公告)日：2016-07-19
申请号：US14723738
申请日：2015-05-28
申请人： Kabushiki Kaisha Toshiba
发明人： Yutaka Onozuka , Hiroshi Yamada , Nobuto Managaki
IPC分类号： H01L23/00 , H01L21/768 , H01L23/31 , H01L23/522 , H01L23/04 , H01L23/48 , H01L23/498 , H01L23/538 , H01L23/532
CPC分类号： H01L24/08 , H01L21/76802 , H01L23/04 , H01L23/3128 , H01L23/3157 , H01L23/481 , H01L23/49816 , H01L23/49894 , H01L23/5226 , H01L23/5329 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L2224/0401 , H01L2224/04105 , H01L2224/05025 , H01L2224/05083 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/12105 , H01L2224/24137 , H01L2924/0665 , H01L2924/07025 , H01L2924/12
摘要： According to an embodiment, a semiconductor device comprises an insulative resin, an interconnect, a plurality of semiconductor elements, a first conductive unit, a first connector, and a first metal layer. The insulative resin includes a first region and a second region. At least a portion of the interconnect is arranged with at least a portion of the first region in a first direction. The first conductive unit pierces the second region in the first direction. At least a portion of the first connector is arranged with at least a portion of the first conductive unit in the first direction. At least a portion of the first connector is arranged with at least a portion of the interconnect in a second direction intersecting the first direction. The first metal layer is provided between the first conductive unit and the first connector. The first metal layer contacts the insulative resin.
摘要翻译：根据实施例，半导体器件包括绝缘树脂，互连件，多个半导体元件，第一导电单元，第一连接器和第一金属层。绝缘树脂包括第一区域和第二区域。互连的至少一部分被布置成具有第一方向的第一区域的至少一部分。第一导电单元沿第一方向刺穿第二区域。第一连接器的至少一部分布置成具有第一导电单元的至少一部分在第一方向上。第一连接器的至少一部分布置成具有与第一方向交叉的第二方向的互连的至少一部分。第一金属层设置在第一导电单元和第一连接器之间。第一金属层接触绝缘树脂。

7. 发明申请

US20150084208A1 CONNECTION MEMBER, SEMICONDUCTOR DEVICE, AND STACKED STRUCTURE 有权
标题翻译：连接构件，半导体器件和堆叠结构
公开(公告)号：US20150084208A1
公开(公告)日：2015-03-26
申请号：US14466493
申请日：2014-08-22
申请人： Kabushiki Kaisha Toshiba
发明人： Atsuko IIDA , Tadahiro Sasaki , Nobuto Managaki , Yutaka Onozuka , Hiroshi Yamada
IPC分类号： H01L23/522 , H01L23/00
CPC分类号： H01L23/49827 , H01L23/04 , H01L23/49822 , H01L23/5389 , H01L23/60 , H01L23/66 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/95 , H01L24/96 , H01L25/0657 , H01L2223/6616 , H01L2223/6627 , H01L2223/6677 , H01L2223/6683 , H01L2224/02311 , H01L2224/02371 , H01L2224/02381 , H01L2224/0239 , H01L2224/0345 , H01L2224/0401 , H01L2224/04105 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/12105 , H01L2224/16225 , H01L2224/2101 , H01L2224/2105 , H01L2224/211 , H01L2224/214 , H01L2224/24195 , H01L2224/82106 , H01L2224/95 , H01L2224/96 , H01L2225/0652 , H01L2225/06548 , H01L2924/15788 , H01L2924/19105 , H01P1/20 , H01P1/2005 , H01P1/202 , H01P5/028 , H05K1/117 , H05K3/403 , H05K2201/0919 , H01L2924/00 , H01L2224/19 , H01L2224/03 , H01L2924/00014 , H01L2224/0231 , H01L2924/01013 , H01L2924/01029 , H01L2924/01079
摘要： A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.
摘要翻译：根据实施例的连接构件包括电介质材料，穿透介电材料的穿透通孔，设置在介电材料中的第一金属平面，第一金属平面垂直于穿透通孔的延伸方向，第一金属平面穿过穿透孔的第二金属平面和与穿透通孔的延伸方向平行地设置在电介质材料上的第二金属平面，连接到第一金属平面的第二金属平面。

8. 发明申请

US20140091447A1 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140091447A1
公开(公告)日：2014-04-03
申请号：US14023712
申请日：2013-09-11
申请人： Kabushiki Kaisha Toshiba
发明人： Yutaka ONOZUKA , Hiroshi Yamada , Kazuhiko Itaya
IPC分类号： H01L23/495 , H01L21/78
CPC分类号： H01L23/49575 , H01L21/561 , H01L21/568 , H01L21/78 , H01L23/3121 , H01L23/3135 , H01L23/49838 , H01L23/5389 , H01L23/64 , H01L24/24 , H01L24/82 , H01L25/16 , H01L2224/04105 , H01L2224/24195 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49171 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire.
摘要翻译：根据实施例的半导体器件包括：第一单元器件，被配置为包括半导体芯片，与半导体芯片的背面接触的背面电极和其一端连接到背面电极的接合线; 被配置为具有与所述第一单元设备的功能不同的功能的第二单元设备; 树脂层，被配置为将所述第一和第二单元装置彼此固定; 以及形成在半导体芯片的表面侧的树脂层上并与接合线的另一端连接的第一布线。

9. 发明申请

US20140028412A1 EBG STRUCTURE AND CIRCUIT BOARD 有权
标题翻译： EBG结构和电路板
公开(公告)号：US20140028412A1
公开(公告)日：2014-01-30
申请号：US13951875
申请日：2013-07-26
申请人： Kabushiki Kaisha Toshiba
发明人： Tadahiro Sasaki , Kazuhiko Itaya , Hiroshi Yamada
IPC分类号： H04B3/28 , H03H7/01
CPC分类号： H03H7/0138 , H01L2924/0002 , H05K1/0236 , H01L2924/00
摘要： An EBG (Electromagnetic Band Gap) structure according to an embodiment includes: an electrode that is made of a first conductor; a first insulating layer that is provided on the electrode; a patch unit that is provided in substantially parallel with the electrode on the first insulating layer, the patch unit including a first gap, the patch unit being made of a second conductor; a second insulating layer that is provided on the patch unit; a first via that is provided between the patch unit in the first insulating layer and the electrode and connected to the patch unit and the electrode; and a second via that is provided in the first and second insulating layers, the second via piercing the first gap and being connected to the electrode.
摘要翻译：根据实施例的EBG（电磁带隙）结构包括：由第一导体制成的电极; 设置在电极上的第一绝缘层; 贴片单元，与所述第一绝缘层上的所述电极基本平行地设置，所述贴片单元包括第一间隙，所述贴片单元由第二导体制成; 设置在所述贴片单元上的第二绝缘层; 第一通孔，其设置在第一绝缘层中的贴片单元和电极之间并连接到贴片单元和电极; 以及设置在所述第一绝缘层和所述第二绝缘层中的第二通孔，所述第二通孔刺穿所述第一间隙并连接到所述电极。

10. 发明授权

US09468089B2 EBG structure, semiconductor device, and circuit board 有权
标题翻译： EBG结构，半导体器件和电路板
公开(公告)号：US09468089B2
公开(公告)日：2016-10-11
申请号：US14460694
申请日：2014-08-15
申请人： Kabushiki Kaisha Toshiba
发明人： Tadahiro Sasaki , Hiroshi Yamada
IPC分类号： H04B3/28 , H05K1/02 , H01L23/00 , H01L23/498
CPC分类号： H05K1/0236 , H01L23/49822 , H01L23/49838 , H01L24/19 , H01L2224/04105 , H01L2224/16225 , H01L2224/16235 , H01L2224/24137 , H01L2924/1531 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H05K1/0225 , H05K1/0231 , H05K1/0233 , H05K1/0242 , H05K1/0243 , H05K1/0298 , H05K2201/0715 , H05K2201/09254 , H05K2201/0969 , H05K2201/09727
摘要： An EBG structure of an embodiment includes an electrode plane, a first insulating layer provided on the electrode plane, a first metal patch provided on the first insulating layer, a second metal patch provided on the first insulating layer, a second insulating layer provided on the first and second metal patches, an interconnect layer provided on the second insulating layer, a third insulating layer provided on the interconnect layer, a first via connected to the electrode plane and the first metal patch, and a second via connected to the electrode plane and the second metal patch. The second metal patch is separately adjacent to the first metal patch. The interconnect layer has a first opening and a second opening. The first via penetrates through the first opening. The second via penetrates through the second opening.
摘要翻译：实施例的EBG结构包括电极平面，设置在电极平面上的第一绝缘层，设置在第一绝缘层上的第一金属贴片，设置在第一绝缘层上的第二金属贴片，设置在第一绝缘层上的第二绝缘层第一和第二金属贴片，设置在第二绝缘层上的互连层，设置在互连层上的第三绝缘层，连接到电极平面和第一金属贴片的第一通孔，以及连接到电极平面的第二通孔和第二个金属贴片。第二金属贴片与第一金属贴片分开相邻。互连层具有第一开口和第二开口。第一个通孔穿过第一个开口。第二通孔穿过第二开口。

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