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1. 发明授权

US09748337B2 Semiconductor memory device 有权
公开(公告)号：US09748337B2
公开(公告)日：2017-08-29
申请号：US14849737
申请日：2015-09-10
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeki Kobayashi , Mitsuru Sato , Tomohiro Yamada
IPC分类号： H01L29/792 , H01L29/66 , H01L27/115 , H01L29/10 , H01L27/11582 , H01L21/28 , H01L29/06
CPC分类号： H01L29/1037 , H01L21/28282 , H01L27/11582 , H01L29/0676
摘要： Three directions intersecting each other are referred to as first to third directions. A semiconductor memory device according to embodiments includes a semiconductor substrate having a top surface spread in the first and second directions, and a plurality of conductive layers laminated at predetermined intervals in the third direction on the semiconductor substrate. The semiconductor memory device further includes a columnar semiconductor layer having an interface that is in contact with the semiconductor substrate on a side surface. The columnar semiconductor layer is opposed to the plurality of conductive layers. The columnar semiconductor layer has the third direction as a lengthwise direction. The interface exists in a position deeper than the top surface of the semiconductor substrate in the third direction.

2. 发明申请

US20150372006A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20150372006A1
公开(公告)日：2015-12-24
申请号：US14724853
申请日：2015-05-29
申请人： Kabushiki Kaisha Toshiba
发明人： Masaru Kito , Hideaki Aochi , Ryota Katsumata , Akihiro Nitayama , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka , Mitsuru Sato
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11556 , H01L27/11573 , H01L27/11578
摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
摘要翻译：提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

3. 发明授权

US09054132B2 Method for manufacturing semiconductor device and semiconductor device 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US09054132B2
公开(公告)日：2015-06-09
申请号：US13930401
申请日：2013-06-28
申请人： Kabushiki Kaisha Toshiba
发明人： Mitsuru Sato , Masaru Kito , Megumi Ishiduki , Ryota Katsumata
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L27/115 , H01L29/792 , H01L29/06
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/0657 , H01L29/42344 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.
摘要翻译：根据一个实施例，公开了一种用于制造半导体器件的方法。第二绝缘膜密封绝缘层和选择栅极的界面附近的孔。第二绝缘膜设置在通道主体的侧壁上，在选通门上方的孔中留有空间。该方法可以包括在该空间内埋入半导体膜，此外，形成与通道体接触的导电膜。

4. 发明申请

US20140284694A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20140284694A1
公开(公告)日：2014-09-25
申请号：US14020254
申请日：2013-09-06
申请人： Kabushiki Kaisha Toshiba
发明人： Soichirou Kitazaki , Mitsuru Sato
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/66833 , H01L27/11582 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body, each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the stacked body; an interlayer insulating film provided on the stacked body; a gate electrode provided on the interlayer insulating film; a semiconductor layer extending from an upper end of the gate electrode to a lower face of the stacked body; a first insulating film provided between the semiconductor layer and each of the plurality of electrode layers and including at least one layer of a nitride film; and a second insulating film provided between the gate electrode and the semiconductor layer and including at least one layer of a nitride film, a film thickness of at least a part of the second insulating film being thinner than a film thickness of the first insulating film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括：堆叠体，多个电极层中的每一个和多个绝缘层中的每一个交替堆叠在堆叠体中; 设置在层叠体上的层间绝缘膜; 设置在层间绝缘膜上的栅电极; 半导体层，其从所述栅电极的上端延伸到所述层叠体的下表面; 设置在所述半导体层与所述多个电极层中的每一个之间并且包括至少一层氮化物膜的第一绝缘膜; 以及设置在所述栅电极和所述半导体层之间并且包括至少一层氮化物膜的第二绝缘膜，所述第二绝缘膜的至少一部分的膜厚比所述第一绝缘膜的膜厚薄。

5. 发明授权

US09373634B2 Method for manufacturing semiconductor device and semiconductor device 有权
公开(公告)号：US09373634B2
公开(公告)日：2016-06-21
申请号：US14707774
申请日：2015-05-08
申请人： Kabushiki Kaisha Toshiba
发明人： Mitsuru Sato , Masaru Kito , Megumi Ishiduki , Ryota Katsumata
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66 , H01L29/78 , H01L29/423 , H01L29/06
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/0657 , H01L29/42344 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.

6. 发明授权

US09466667B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09466667B2
公开(公告)日：2016-10-11
申请号：US14641051
申请日：2015-03-06
申请人： Kabushiki Kaisha Toshiba
发明人： Soichirou Kitazaki , Mitsuru Sato , Megumi Ishiduki
IPC分类号： H01L29/06 , H01L29/788 , H01L29/51 , H01L21/3213 , H01L27/115 , H01L21/28 , H01L29/792 , H01L29/66 , H01L29/423
CPC分类号： H01L29/0649 , H01L21/28008 , H01L21/28273 , H01L21/32133 , H01L27/11521 , H01L27/11568 , H01L27/1157 , H01L27/11582 , H01L29/42324 , H01L29/4234 , H01L29/513 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/792
摘要： According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers separately stacked each other; a plurality of columnar sections provided in the stacked body and extending in a stacking direction of the stacked body; and a first insulating section separating the stacked body. The respective columnar sections include a semiconductor body extending in the stacking direction; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. The first insulating section includes a first air gap.
摘要翻译：根据一个实施例，半导体存储器件包括：层叠体，其包括彼此分开堆叠的多个电极层; 设置在所述层叠体中并在所述层叠体的堆叠方向上延伸的多个柱状部; 以及分离所述层叠体的第一绝缘部。相应的柱状部分包括沿堆叠方向延伸的半导体本体; 以及设置在所述半导体主体和所述多个电极层之间的电荷存储膜。第一绝缘部分包括第一气隙。

7. 发明授权

US08748300B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08748300B2
公开(公告)日：2014-06-10
申请号：US14048495
申请日：2013-10-08
申请人： Kabushiki Kaisha Toshiba
发明人： Megumi Ishiduki , Ryota Katsumata , Tomo Ohsawa , Mitsuru Sato , Masaru Kidoh , Hiroyasu Tanaka
IPC分类号： H01L21/425 , H01L29/792
CPC分类号： H01L21/425 , H01L27/11582 , H01L29/7926
摘要： According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.
摘要翻译：根据一个实施例，半导体器件包括衬底，第一层叠体，存储膜，第一通道体，第二堆叠体，栅极绝缘膜和第二通道体。在选择栅极的侧面和第二绝缘层之间形成台阶部。覆盖第二通道体的台阶部分的部分的膜厚比设置在第二通道体的第二绝缘层之间的部分的膜厚度厚。

8. 发明申请

US20140001544A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20140001544A1
公开(公告)日：2014-01-02
申请号：US13930401
申请日：2013-06-28
申请人： Kabushiki Kaisha Toshiba
发明人： Mitsuru Sato , Masaru Kito , Megumi Ishiduki , Ryota Katsumata
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/0657 , H01L29/42344 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.
摘要翻译：根据一个实施例，公开了一种用于制造半导体器件的方法。第二绝缘膜密封绝缘层和选择栅极的界面附近的孔。第二绝缘膜设置在通道主体的侧壁上，在选通门上方的孔中留有空间。该方法可以包括在该空间内埋入半导体膜，此外，形成与通道体接触的导电膜。

9. 发明申请

US20170338244A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20170338244A1
公开(公告)日：2017-11-23
申请号：US15666653
申请日：2017-08-02
申请人： Kabushiki Kaisha Toshiba
发明人： Masaru Kito , Hideaki Aochi , Ryota Katsumata , Akihiro Nitayama , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka , Mitsuru Sato
IPC分类号： H01L27/11582 , H01L27/11573 , H01L27/11556 , H01L27/105 , H01L27/06 , H01L21/822 , H01L27/11578 , H01L27/115 , G11C16/04
CPC分类号： H01L27/11582 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11556 , H01L27/11573 , H01L27/11578
摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

10. 发明授权

US09748260B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
公开(公告)号：US09748260B2
公开(公告)日：2017-08-29
申请号：US14724853
申请日：2015-05-29
申请人： Kabushiki Kaisha Toshiba
发明人： Masaru Kito , Hideaki Aochi , Ryota Katsumata , Akihiro Nitayama , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka , Mitsuru Sato
IPC分类号： H01L29/78 , H01L27/11582 , H01L21/822 , H01L27/06 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L27/11578 , H01L27/11556 , G11C16/04
CPC分类号： H01L27/11582 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11556 , H01L27/11573 , H01L27/11578
摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

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