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1. 发明授权

US08879349B2 Storage device 有权
标题翻译：储存设备
公开(公告)号：US08879349B2
公开(公告)日：2014-11-04
申请号：US13960186
申请日：2013-08-06
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichiro Yoshii , Ikuo Magaki , Naoto Oshiyama , Tokumasa Hara , Akira Yamaga , Ryo Yamaki , Kenta Yasufuku , Naomi Takeda , Yu Nakanishi , Arata Miyamoto , Naoaki Kokubun , Daisuke Iwai
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C5/14 , G11C16/30
摘要： A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.
摘要翻译：根据实施例的存储装置包括第一和第二非易失性半导体存储器。此外，存储设备包括控制第一非易失性存储器以使第一非易失性存储器执行处理的第一控制器。此外，存储设备包括控制第二非易失性存储器以使第二非易失性存储器执行处理的第二控制器。存储装置还包括连接到第一控制器和第二控制器的信号线，通过该信号线在第一控制器和第二控制器之间传送令牌。第一控制器能够在保持令牌的同时控制第一非易失性存储器，并且第二控制器能够在保持令牌的同时控制第二非易失性存储器。

2. 发明申请

US20140068378A1 SEMICONDUCTOR STORAGE DEVICE AND MEMORY CONTROLLER 审中-公开
标题翻译：半导体存储器件和存储器控制器
公开(公告)号：US20140068378A1
公开(公告)日：2014-03-06
申请号：US13772659
申请日：2013-02-21
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenichiro YOSHII , Naoaki Kokubun , Naoto Oshiyama , Ryo Yamaki , Ikuo Magaki , Kenta Yasufuku , Akira Yamaga
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1012 , H03M13/152 , H03M13/1525 , H03M13/154
摘要： According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data.
摘要翻译：根据实施例，半导体存储装置包括存储器，产生奇偶校验的编码单元和包括校正子计算单元，错误位置多项式计算单元和错误搜索和校正单元的解码单元，并且执行基于数据的错误纠正处理和从存储器读取的奇偶校验。在执行压缩处理时，当通过错误位置多项式获取的错误位的数量等于或小于基于有效数据的第一阈值时，不执行错误搜索和校正单元的处理。

3. 发明申请

US20160077737A1 INFORMATION PROCESSING APPARATUS AND MEMORY SYSTEM 审中-公开
标题翻译：信息处理设备和存储系统
公开(公告)号：US20160077737A1
公开(公告)日：2016-03-17
申请号：US14638441
申请日：2015-03-04
申请人： Kabushiki Kaisha Toshiba
发明人： Masanori YAMATO , Shigenori Sugimoto , Toshio Fujisawa , Naoto Oshiyama
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0679 , G06F13/16 , G06F2206/1014
摘要： According to one embodiment, an information processing apparatus includes a host and a memory system. The host includes a main memory. The memory system includes a memory access unit and an interface unit. The memory access unit converts a first request into transmission information. The first request is a request for data transfer toward a memory region as a part of the main memory. The interface unit transmits transmission information according to an instruction from the memory access unit.
摘要翻译：根据一个实施例，信息处理设备包括主机和存储器系统。主机包含一个主内存。存储器系统包括存储器存取单元和接口单元。存储器访问单元将第一请求转换为传输信息。第一个请求是作为主存储器的一部分向存储器区域传送数据的请求。接口单元根据来自存储器存取单元的指令发送发送信息。

4. 发明授权

US09003269B2 Memory controller and semiconductor storage device 有权
标题翻译：存储控制器和半导体存储设备
公开(公告)号：US09003269B2
公开(公告)日：2015-04-07
申请号：US13837950
申请日：2013-03-15
申请人： Kabushiki Kaisha Toshiba
发明人： Naoto Oshiyama , Ryo Yamaki , Kenta Yasufuku , Naoaki Kokubun
IPC分类号： H03M13/00 , G06F11/10 , H03M13/29 , H03M13/15
CPC分类号： G06F11/10 , G06F11/1048 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/154 , H03M13/1545 , H03M13/2906 , H03M13/2927 , H03M13/6502 , H03M13/6561
摘要： According to one embodiment, a decoder of a memory controller includes: a syndrome calculating unit configured to calculate a syndrome based upon a code word read from the memory; an error locator polynomial generating unit configured to generate an error locator polynomial based upon the syndrome, and to obtain a number of errors based upon the generated error locator polynomial; and an error location calculating unit configured to calculate an error location based upon the error locator polynomial, wherein the process of the error location calculating unit is not executed, when the number of errors is not less than the maximum number of bits that can be corrected by the error locator polynomial generating unit.
摘要翻译：根据一个实施例，存储器控制器的解码器包括：校正子计算单元，被配置为基于从存储器读取的代码字来计算校正子; 错误定位器多项式生成单元，被配置为基于所述校正子生成错误定位器多项式，并且基于所生成的误差定位器多项式来获得多个误差; 以及误差位置计算单元，被配置为基于所述误差定位器多项式来计算误差位置，其中当所述误差数量不小于可校正的最大位数时，所述错误位置计算单元的处理不被执行由误差定位器多项式生成单元。

5. 发明授权

US09003261B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US09003261B2
公开(公告)日：2015-04-07
申请号：US14017246
申请日：2013-09-03
申请人： Kabushiki Kaisha Toshiba
发明人： Ikuo Magaki , Naoto Oshiyama , Kenichiro Yoshii , Kosuke Hatsuda , Shirou Fujita , Tokumasa Hara , Kohei Oikawa , Kenta Yasufuku
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1008 , G06F11/1012
摘要： A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host.
摘要翻译：存储器系统包括第一非易失性存储器，具有比第一非易失性存储器更长的访问延迟的第二非易失性存储器，第一纠错单元，第二纠错单元和接口。第一非易失性存储器存储为第一数据生成的第一数据和第一纠错码。第二非易失性存储器存储对于具有比第一纠错码更高的校正能力的第一数据产生的第二纠错码。第一纠错单元通过使用第一纠错码对第一数据进行纠错。第二纠错单元通过使用第二纠错码对第一数据进行纠错。接口将纠错后的第一个数据发送给主机。

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