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1. 发明授权

US09239798B2 Prefetcher with arbitrary downstream prefetch cancelation 有权
标题翻译：预取器具有任意下行预取取消
公开(公告)号：US09239798B2
公开(公告)日：2016-01-19
申请号：US13233028
申请日：2011-09-15
申请人： Matthew D Pierson , Joseph R M Zbiciak , Kai Chirca , Amitabh Menon , Timothy D Anderson
发明人： Matthew D Pierson , Joseph R M Zbiciak , Kai Chirca , Amitabh Menon , Timothy D Anderson
IPC分类号： G06F12/00 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.
摘要翻译：预取消除仲裁器通过任意取消推测性预取来改善对共享存储器资源的访问。预取消除仲裁器将一组任意策略应用于推测预取以选择一个或多个接收到的推测性预取以取消。所选择的推测预取被取消，并且每个取消的推测预取的取消通知被发送到诸如与取消的推测预取相关联的处理器本地的预取单元或本地存储器仲裁器的更高级存储器组件。该组任意策略用于减少对共享内存资源的内存访问。

2. 发明授权

US08977819B2 Prefetch stream filter with FIFO allocation and stream direction prediction 有权
标题翻译：使用FIFO分配和流方向预测预取流过滤器
公开(公告)号：US08977819B2
公开(公告)日：2015-03-10
申请号：US13213024
申请日：2011-08-18
申请人： Kai Chirca , Joseph R M Zbiciak , Matthew D Pierson , Timothy D Anderson
发明人： Kai Chirca , Joseph R M Zbiciak , Matthew D Pierson , Timothy D Anderson
IPC分类号： G06F12/00 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： A prefetch filter receives a memory read request having an associated address for accessing data that is stored in a line of memory. An address window is determined that has an address range that encompasses an address space that is twice as large as the line of memory. In response to a determination of in which half the address window includes the requested line of memory, a prefetch direction is to a first direction or to an opposite direction. The prefetch filter can include an array of slots for storing a portion of a next predicted access and determine a memory stream in response to a hit on the array by a subsequent memory request. The prefetch filter FIFO counter cycles through the slots of the array before wrapping around to a first slot of the array for storing a next predicted address portion.
摘要翻译：预取过滤器接收具有用于访问存储在存储器行中的数据的相关联地址的存储器读请求。确定地址窗口具有包含地址空间的地址范围，该地址空间是存储器行的两倍。响应于地址窗口的哪一半包括所请求的存储器行的确定，预取方向是第一方向或相反方向。预取过滤器可以包括用于存储下一预测访问的一部分的时隙阵列，并且响应于后续存储器请求对数组的命中来确定存储器流。预取滤波器FIFO计数器在绕到阵列的第一时隙之前循环穿过阵列的时隙以存储下一个预测的地址部分。

3. 发明授权

US08601221B2 Speculation-aware memory controller arbiter 有权
标题翻译：投机感知内存控制器仲裁器
公开(公告)号：US08601221B2
公开(公告)日：2013-12-03
申请号：US13218414
申请日：2011-08-25
申请人： Kai Chirca , Timothy D Anderson , Joseph R M Zbiciak
发明人： Kai Chirca , Timothy D Anderson , Joseph R M Zbiciak
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： A memory arbiter minimizes latency of memory accesses in a system having multiple processors. The memory arbiter improves overall system performance by managing the memory requests from each processor individually before those requests are sent to a central memory arbiter for handling memory requests for the shared resources from the multiple processors. The local memory arbiter buffers the memory requests from a local processor, analyzes the buffered memory requests, and optimizes the requests by reordering commands according to a rule set, and by performing write merging and prefetch squashing in certain conditions.
摘要翻译：存储器仲裁器最小化具有多个处理器的系统中的存储器访问的延迟。存储器仲裁器通过在将这些请求发送到中央存储器仲裁器来处理来自多个处理器的共享资源的存储器请求之前单独管理来自每个处理器的存储器请求来提高整体系统性能。本地存储器仲裁器缓冲来自本地处理器的存储器请求，分析缓冲的存储器请求，并且通过根据规则集重新排序命令来优化请求，并且通过在某些条件下执行写入合并和预取压缩。

4. 发明授权

US09898415B2 Slot/sub-slot prefetch architecture for multiple memory requestors 有权
公开(公告)号：US09898415B2
公开(公告)日：2018-02-20
申请号：US13233443
申请日：2011-09-15
申请人： Kai Chirca , Joseph R M Zbiciak , Matthew D Pierson
发明人： Kai Chirca , Joseph R M Zbiciak , Matthew D Pierson
IPC分类号： G06F12/00 , G06F12/0897 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F9/38
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

5. 发明授权

US09009414B2 Prefetch address hit prediction to reduce memory access latency 有权
标题翻译：预取地址命中预测以减少内存访问延迟
公开(公告)号：US09009414B2
公开(公告)日：2015-04-14
申请号：US13212980
申请日：2011-08-18
申请人： Timothy D Anderson , Joseph R M Zbiciak , Matthew D Pierson
发明人： Timothy D Anderson , Joseph R M Zbiciak , Matthew D Pierson
IPC分类号： G06F12/00 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： A prefetch unit receives a memory read request having an associated address for accessing data that is stored in memory. A next predicted address is determined in response to a prefetch address stored in a slot of an array for storing portions of predicted addresses and associated with a slot in accordance with an order in which a prefetch FIFO counter is modified to select the slots of the array. Data is prefetched from a lower-level hierarchical memory in accordance with a next predicted address and provisioned the prefetched data to minimize a read time for reading the prefetched data. The provisioned prefetched data is read-out when the address of the memory request is associated with the next predicted address.
摘要翻译：预取单元接收具有用于访问存储在存储器中的数据的相关联地址的存储器读取请求。响应于存储在用于存储预测地址的部分并且与时隙相关联的阵列的时隙中的预取地址，根据修改预取FIFO计数器以选择阵列的时隙的顺序来确定下一预测地址。根据下一个预测的地址从低级分层存储器预取数据，并提供预取的数据以最小化读取预取数据的读取时间。当存储器请求的地址与下一预测地址相关联时，所提供的预取数据被读出。

6. 发明授权

US08788759B2 Double-buffered data storage to reduce prefetch generation stalls 有权
标题翻译：双缓冲数据存储，以减少预取生成档位
公开(公告)号：US08788759B2
公开(公告)日：2014-07-22
申请号：US13223237
申请日：2011-08-31
申请人： Matthew D Pierson , Joseph R M Zbiciak
发明人： Matthew D Pierson , Joseph R M Zbiciak
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： A prefetch unit includes a program prefetch address generator that receives memory read requests and in response to addresses associated with the memory read request generates prefetch addresses and stores the prefetch addresses in slots of the prefetch unit buffer. Each slot includes a buffer for storing a prefetch address, two data buffers for storing data that is prefetched using the prefetch address of the slot, and a data buffer selector for alternating the functionality of the two data buffers. A first buffer is used to hold data that is returned in response to a received memory request, and a second buffer is used to hold data from a subsequent prefetch operation having a subsequent prefetch address, such that the data in the first buffer is not overwritten even when the data in the first buffer is still in the process of being read out.
摘要翻译：预取单元包括程序预取地址发生器，其接收存储器读请求，并响应于与存储器读请求相关联的地址产生预取地址，并将预取地址存储在预取单元缓冲器的时隙中。每个时隙包括用于存储预取地址的缓冲器，用于存储使用时隙的预取地址预取的数据的两个数据缓冲器，以及用于交替两个数据缓冲器的功能的数据缓冲器选择器。第一缓冲器用于保存响应于所接收的存储器请求返回的数据，并且第二缓冲器用于保存来自具有后续预取地址的后续预取操作的数据，使得第一缓冲器中的数据不被覆盖即使第一缓冲器中的数据仍处于读出的过程中。

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