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1. 发明授权

US09337132B2 Methods and configuration for manufacturing flip chip contact (FCC) power package 有权
标题翻译：制造倒装芯片接触（FCC）电源封装的方法和配置
公开(公告)号：US09337132B2
公开(公告)日：2016-05-10
申请号：US14052711
申请日：2013-10-12
申请人： Ming Sun , Kai Liu , Xiaotian Zhang , Yueh Se Ho , Leeshawn Luo
发明人： Ming Sun , Kai Liu , Xiaotian Zhang , Yueh Se Ho , Leeshawn Luo
IPC分类号： H01L23/495 , H01L29/78 , H01L23/00 , H01L29/66 , H01L23/492
CPC分类号： H01L23/49562 , H01L23/492 , H01L23/4928 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/83 , H01L24/97 , H01L29/66477 , H01L29/78 , H01L2224/291 , H01L2224/32245 , H01L2224/33181 , H01L2224/83205 , H01L2224/83801 , H01L2224/8385 , H01L2224/83895 , H01L2224/97 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2224/83 , H01L2924/014
摘要： A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.
摘要翻译：用于容纳，保护和提供用于功率晶体管的电触头的功率器件封装包括用于直接不连接到功率晶体管的顶部和底部引线框架。功率晶体管作为具有源极接触的倒装芯片附接到底部引线框架，并且栅极接触件直接地不连接到底部引线框架上。功率晶体管具有附接到顶部引线框架的底部漏极接触。顶部引线框架还包括用于提供与底部引线框架基本上在同一侧上的底部漏极电极的延伸部分。在优选实施例中，功率器件封装还包括通过施加超声波能量的源极，栅极或漏极以及顶部或底部引线框架的器件金属之间的接合层。

2. 发明申请

US20090233403A1 DUAL FLAT NON-LEADED SEMICONDUCTOR PACKAGE 有权
标题翻译：双平面非引线半导体封装
公开(公告)号：US20090233403A1
公开(公告)日：2009-09-17
申请号：US12474089
申请日：2009-05-28
申请人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
发明人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
IPC分类号： H01L21/60
CPC分类号： H01L24/48 , H01L23/3107 , H01L23/4952 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/45 , H01L24/49 , H01L24/83 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/05599 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48799 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/0665 , H01L2924/00012
摘要： A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.
摘要翻译： DFN半导体封装包括引线框架，其具有与漏极引线，栅极引线和源极引线一体形成的管芯焊接焊盘，耦合到管芯焊接焊盘的管芯，耦合到源极引线的管芯源极接合区域和管芯栅极键合区域，以及密封剂，其至少部分地覆盖晶片，漏极引线，栅极引线和源极引线。

3. 发明申请

US20060145312A1 Dual flat non-leaded semiconductor package 审中-公开
标题翻译：双平面无铅半导体封装
公开(公告)号：US20060145312A1
公开(公告)日：2006-07-06
申请号：US11029653
申请日：2005-01-05
申请人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
发明人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/49113 , H01L2224/49171 , H01L2224/4943 , H01L2224/85 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.
摘要翻译： DFN半导体封装包括引线框架，其具有与漏极引线，栅极引线和源极引线一体形成的管芯焊接焊盘，耦合到管芯焊接焊盘的管芯，耦合到源极引线的管芯源极接合区域和管芯栅极键合区域，以及密封剂，其至少部分地覆盖晶片，漏极引线，栅极引线和源极引线。

4. 发明授权

US07951651B2 Dual flat non-leaded semiconductor package 有权
标题翻译：双平面无铅半导体封装
公开(公告)号：US07951651B2
公开(公告)日：2011-05-31
申请号：US12474089
申请日：2009-05-28
申请人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
发明人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
IPC分类号： H01L21/00
CPC分类号： H01L24/48 , H01L23/3107 , H01L23/4952 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/45 , H01L24/49 , H01L24/83 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/05599 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48799 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/0665 , H01L2924/00012
摘要： A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.
摘要翻译： DFN半导体封装包括引线框架，其具有与漏极引线，栅极引线和源极引线一体形成的管芯焊接焊盘，耦合到管芯焊接焊盘的管芯，耦合到源极引线的管芯源极接合区域和管芯栅极键合区域，以及密封剂，其至少部分地覆盖晶片，漏极引线，栅极引线和源极引线。

5. 发明授权

US07897438B2 Method of making semiconductor package with plated connection 有权
标题翻译：制造具有电镀连接的半导体封装的方法
公开(公告)号：US07897438B2
公开(公告)日：2011-03-01
申请号：US12154537
申请日：2008-05-22
申请人： Leeshawn Luo , Kai Liu , Ming Sun , Xiao Tian Zhang
发明人： Leeshawn Luo , Kai Liu , Ming Sun , Xiao Tian Zhang
IPC分类号： H01L21/00
CPC分类号： H01L21/568 , H01L23/3107 , H01L23/4334 , H01L23/49524 , H01L24/40 , H01L24/73 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16245 , H01L2224/40095 , H01L2224/40245 , H01L2224/73253 , H01L2224/73255 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/37099 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.
摘要翻译：公开了半导体封装和制造半导体封装的方法。半导体封装具有顶表面和安装表面，并且包括管芯，导电连接材料，电镀材料和绝缘材料。模具具有朝向半导体封装的安装表面的处理表面。暴露的金属连接处于模具的加工表面。导电连接材料设置在暴露的金属连接上。电镀材料与导电连接材料接触。绝缘材料围绕导电连接材料形成，电镀材料延伸到绝缘材料的外部。

6. 发明申请

US20060180931A1 Semiconductor package with plated connection 有权
标题翻译：半导体封装带电镀连接
公开(公告)号：US20060180931A1
公开(公告)日：2006-08-17
申请号：US11058913
申请日：2005-02-15
申请人： Leeshawn Luo , Kai Liu , Ming Sun , Xiao Zhang
发明人： Leeshawn Luo , Kai Liu , Ming Sun , Xiao Zhang
IPC分类号： H01L23/52
CPC分类号： H01L21/568 , H01L23/3107 , H01L23/4334 , H01L23/49524 , H01L24/40 , H01L24/73 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16245 , H01L2224/40095 , H01L2224/40245 , H01L2224/73253 , H01L2224/73255 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/37099 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.
摘要翻译：公开了半导体封装和制造半导体封装的方法。半导体封装具有顶表面和安装表面，并且包括管芯，导电连接材料，电镀材料和绝缘材料。模具具有朝向半导体封装的安装表面的处理表面。暴露的金属连接处于模具的加工表面。导电连接材料设置在暴露的金属连接上。电镀材料与导电连接材料接触。绝缘材料围绕导电连接材料形成，电镀材料延伸到绝缘材料的外部。

7. 发明授权

US07394151B2 Semiconductor package with plated connection 有权
公开(公告)号：US07394151B2
公开(公告)日：2008-07-01
申请号：US11058913
申请日：2005-02-15
申请人： Leeshawn Luo , Kai Liu , Ming Sun , Xiao Tian Zhang
发明人： Leeshawn Luo , Kai Liu , Ming Sun , Xiao Tian Zhang
IPC分类号： H01L23/48
CPC分类号： H01L21/568 , H01L23/3107 , H01L23/4334 , H01L23/49524 , H01L24/40 , H01L24/73 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16245 , H01L2224/40095 , H01L2224/40245 , H01L2224/73253 , H01L2224/73255 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/37099 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.

8. 发明申请

US20080233679A1 Semiconductor package with plated connection 有权
标题翻译：半导体封装带电镀连接
公开(公告)号：US20080233679A1
公开(公告)日：2008-09-25
申请号：US12154537
申请日：2008-05-22
申请人： Leeshawn Luo , Kai Liu , Ming Sun , Xiao Tian Zhang
发明人： Leeshawn Luo , Kai Liu , Ming Sun , Xiao Tian Zhang
IPC分类号： H01L21/58
CPC分类号： H01L21/568 , H01L23/3107 , H01L23/4334 , H01L23/49524 , H01L24/40 , H01L24/73 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16245 , H01L2224/40095 , H01L2224/40245 , H01L2224/73253 , H01L2224/73255 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/37099 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.
摘要翻译：公开了半导体封装和制造半导体封装的方法。半导体封装具有顶表面和安装表面，并且包括管芯，导电连接材料，电镀材料和绝缘材料。模具具有朝向半导体封装的安装表面的处理表面。暴露的金属连接处于模具的加工表面。导电连接材料设置在暴露的金属连接上。电镀材料与导电连接材料接触。绝缘材料围绕导电连接材料形成，电镀材料延伸到绝缘材料的外部。

9. 发明申请

US20080211070A1 Flip chip contact (FCC) power package 有权
标题翻译：倒装芯片接触（FCC）电源封装
公开(公告)号：US20080211070A1
公开(公告)日：2008-09-04
申请号：US11894240
申请日：2008-03-31
申请人： Ming Sun , Kai Liu , Xiao Tian Zhang , Yueh Se Ho , Leeshawn Luo
发明人： Ming Sun , Kai Liu , Xiao Tian Zhang , Yueh Se Ho , Leeshawn Luo
IPC分类号： H01L23/495
CPC分类号： H01L29/7813 , H01L24/33 , H01L29/045 , H01L29/4236 , H01L29/66734 , H01L29/7811 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.
摘要翻译：本发明公开了一种功率器件封装，用于容纳，保护和提供功率晶体管的电触头。功率器件封装包括用于直接不连接到功率晶体管的顶部和底部引线框架。功率晶体管作为具有源极接触的倒装芯片附接到底部引线框架，并且栅极接触件直接地不连接到底部引线框架上。功率晶体管具有附接到顶部引线框架的底部漏极接触。顶部引线框架还包括用于提供与底部引线框架基本上在同一侧上的底部漏极电极的延伸部分。在优选实施例中，功率器件封装还包括通过施加超声波能量的源极，栅极或漏极以及顶部或底部引线框架的器件金属之间的接合层。在另一个实施方案中，导电环氧树脂或粘合剂层，焊膏，碳糊或其它类型的附着剂用于将功率晶体管附接到顶引线框架和底引线框架之一的直接无凸起。

10. 发明申请

US20150102425A1 FLIP CHIP CONTACT (FCC) POWER PACKAGE 审中-公开
标题翻译： FLIP CHIP CONTACT（FCC）电源封装
公开(公告)号：US20150102425A1
公开(公告)日：2015-04-16
申请号：US14052711
申请日：2013-10-12
申请人： Ming Sun , Kai Liu , Xiao Tian Zhang , Yueh Se Ho , Leeshawn Luo
发明人： Ming Sun , Kai Liu , Xiao Tian Zhang , Yueh Se Ho , Leeshawn Luo
IPC分类号： H01L23/495 , H01L29/78 , H01L29/66 , H01L23/00
CPC分类号： H01L23/49562 , H01L23/492 , H01L23/4928 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/83 , H01L24/97 , H01L29/66477 , H01L29/78 , H01L2224/291 , H01L2224/32245 , H01L2224/33181 , H01L2224/83205 , H01L2224/83801 , H01L2224/8385 , H01L2224/83895 , H01L2224/97 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2224/83 , H01L2924/014
摘要： A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.
摘要翻译：用于容纳，保护和提供用于功率晶体管的电触头的功率器件封装包括用于直接不连接到功率晶体管的顶部和底部引线框架。功率晶体管作为具有源极接触的倒装芯片附接到底部引线框架，并且栅极接触件直接地不连接到底部引线框架上。功率晶体管具有附接到顶部引线框架的底部漏极接触。顶部引线框架还包括用于提供与底部引线框架基本上在同一侧上的底部漏极电极的延伸部分。在优选实施例中，功率器件封装还包括通过施加超声波能量的源极，栅极或漏极以及顶部或底部引线框架的器件金属之间的接合层。

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