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    • 7. 发明授权
    • Computer implemented method for estimating fabrication yield for
semiconductor integrated circuit including memory blocks with redundant
rows and/or columns
    • 用于估计包括具有冗余行和/或列的存储块的半导体集成电路的制造成品率的计算机实现的方法
    • US5946214A
    • 1999-08-31
    • US891586
    • 1997-07-11
    • William D. HeavlinRichard C. KittlerPing Wen
    • William D. HeavlinRichard C. KittlerPing Wen
    • G06F19/00G11C7/00H01L21/66H01L27/105
    • H01L22/20H01L27/105
    • A computer is used to estimate a fabrication yield for a semiconductor product under design which includes a plurality of integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme in the form of redundant rows and/or columns. A bitmap failure analysis of an existing semiconductor product including a plurality of integrated circuit dies having bitmap failure modes that are comparable to those of the product being designed is performed to obtain a number of failed caches. An observed repair rate is computed as a ratio of a number of the failed caches that can be repaired by the predetermined redundancy scheme to the number of failed caches. A model repair rate for the predetermined redundancy scheme which approximates the observed repair rate is computed using a multiple Poisson model including computed average numbers .lambda. of failures for the failure modes respectively. The numbers .lambda. are optimized by minimizing a least squares difference between the observed repair rates and the model repair rates. The fabrication yield is computed as a predetermined function of the model repair rate including scale factor(s) for the circuit on the wafer being designed. The method can be used to select a redundancy scheme for the wafer by computing fabrication yields for a plurality of candidate redundancy schemes, and selecting the redundancy scheme which has the highest return for additional test, manufacturing and design investment.
    • 一种计算机被用于估计下设计的半导体产品,其包括多个集成电路管芯,其中的每一个包括具有在冗余行和/或列的形式的预定冗余方案的存储器高速缓存中的制造成品率。 执行包括具有与正在设计的产品的位图故障模式相当的位图故障模式的多个集成电路管芯的现有半导体产品的位图故障分析以获得多个故障高速缓存。 观察到的修复率被计算为可以由预定冗余方案修复的故障高速缓存的数量与失败高速缓存的数量的比率。 使用包括故障模式的故障的计算平均数λ的多个泊松模型来计算近似观察到的修复率的预定冗余方案的模型修复率。 通过最小化观察到的修复率和模型修复率之间的最小平方差来优化数字λ。 计算制造产量作为模型修复率的预定函数,包括在设计的晶片上的电路的比例因子。 该方法可以用于通过计算多个候选冗余方案的制造产量来选择晶片的冗余方案,并且选择具有最高回报的冗余方案用于额外的测试,制造和设计投资。