专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08629017B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08629017B2
公开(公告)日：2014-01-14
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

2. 发明授权

US08227311B2 Method of forming enhanced capacitance trench capacitor 有权
标题翻译：形成增强型电容沟槽电容器的方法
公开(公告)号：US08227311B2
公开(公告)日：2012-07-24
申请号：US12900095
申请日：2010-10-07
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L21/8242
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：提供一种制造沟槽电容器的方法，其中衬底的半导体区域的材料组成在其中的至少一个分量的量中变化，使得该量在至少两个不同值之间多次与深度交替。例如，半导体合金中的掺杂剂的浓度或第二半导体材料的重量百分比可以在较高和较低值之间的深度之间交替多次。在这种方法中，可以以取决于材料组成的方式蚀刻半导体区域，以形成具有在与半导体区域的主表面的深度方向上起伏的内表面的沟槽。这种方法还可以包括形成具有波状电容器介电层的沟槽电容器，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

3. 发明授权

US08188528B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08188528B2
公开(公告)日：2012-05-29
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

4. 发明申请

US20120086064A1 METHOD OF FORMING ENHANCED CAPACITANCE TRENCH CAPACITOR 有权
标题翻译：形成增强型电容式电容器的方法
公开(公告)号：US20120086064A1
公开(公告)日：2012-04-12
申请号：US12900095
申请日：2010-10-07
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：提供一种制造沟槽电容器的方法，其中衬底的半导体区域的材料组成在其中的至少一个分量的量中变化，使得该量在至少两个不同值之间多次与深度交替。例如，半导体合金中的掺杂剂的浓度或第二半导体材料的重量百分比可以在较高和较低值之间的深度之间交替多次。在这种方法中，可以以取决于材料组成的方式蚀刻半导体区域，以形成具有在与半导体区域的主表面的深度方向上起伏的内表面的沟槽。这种方法还可以包括形成具有波状电容器介电层的沟槽电容器，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

5. 发明授权

US08829585B2 High density memory cells using lateral epitaxy 有权
标题翻译：使用横向外延的高密度记忆细胞
公开(公告)号：US08829585B2
公开(公告)日：2014-09-09
申请号：US13118881
申请日：2011-05-31
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , David M. Fried , Byeong Y. Kim , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , David M. Fried , Byeong Y. Kim , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/92 , H01L27/10829 , H01L27/10861 , H01L27/1203
摘要： In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.
摘要翻译：在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

6. 发明申请

US20120171827A1 STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20120171827A1
公开(公告)日：2012-07-05
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

7. 发明申请

US20090256185A1 METALLIZED CONDUCTIVE STRAP SPACER FOR SOI DEEP TRENCH CAPACITOR 有权
标题翻译：用于SOI深层电容器的金属导电带间隔器
公开(公告)号：US20090256185A1
公开(公告)日：2009-10-15
申请号：US12100018
申请日：2008-04-09
申请人： Kangguo Cheng , Byeong Y. Kim
发明人： Kangguo Cheng , Byeong Y. Kim
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/1203 , H01L29/66181
摘要： A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A portion of the conductive strap spacer is metallized by reacting with a metal to form a strap metal semiconductor alloy region, which is contiguous over the conductive strap spacer and a source region, and may extend to a top surface of the buried insulator layer along a substantially vertical sidewall of the conductive strap spacer. The conductive strap spacer and the strap metal semiconductor alloy region provide a stable electrical connection between the inner electrode of the deep trench capacitor and the source region of the access transistor.
摘要翻译：在位于绝缘体上半导体（SOI）衬底的掩埋绝缘体层的顶表面下方的内部电极上方的掩埋带状空腔内形成导电带隔离件。导电带隔离物的一部分通过与金属反应而金属化，以形成带状金属半导体合金区域，该带状金属半导体合金区域在导电带隔离物和源极区域上是连续的，并且可以沿着掩模绝缘体层的顶表面延伸导电带间隔件的基本垂直的侧壁。导电带间隔件和带状金属半导体合金区域在深沟槽电容器的内部电极和存取晶体管的源极区域之间提供稳定的电连接。

8. 发明授权

US08492821B2 Enhanced capacitance trench capacitor 有权
标题翻译：增强电容沟槽电容
公开(公告)号：US08492821B2
公开(公告)日：2013-07-23
申请号：US13434883
申请日：2012-03-30
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：包括沟槽电容器的集成电路具有半导体区域，其中材料组成在其中至少一个分量的量变化，使得该量在至少两个不同值之间多次交替深度。例如，半导体合金中的掺杂剂的浓度或第二半导体材料（例如锗）的重量百分比可以在较高和较低值之间的深度之间交替多次。沟槽电容器具有波动的电容器介电层，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

9. 发明授权

US08426268B2 Embedded DRAM memory cell with additional patterning layer for improved strap formation 有权
标题翻译：具有附加图形层的嵌入式DRAM存储单元，用于改善表带形成
公开(公告)号：US08426268B2
公开(公告)日：2013-04-23
申请号：US12698293
申请日：2010-02-02
申请人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
发明人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.
摘要翻译：本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。然后蚀刻层状半导体结构。图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。

10. 发明申请

US20120187465A1 ENHANCED CAPACITANCE TRENCH CAPACITOR 有权
标题翻译：增强型电容式电容器
公开(公告)号：US20120187465A1
公开(公告)日：2012-07-26
申请号：US13434883
申请日：2012-03-30
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：包括沟槽电容器的集成电路具有半导体区域，其中材料组成在其中至少一个分量的量变化，使得该量在至少两个不同值之间多次交替深度。例如，半导体合金中的掺杂剂的浓度或第二半导体材料（例如锗）的重量百分比可以在较高和较低值之间的深度之间交替多次。沟槽电容器具有波动的电容器介电层，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式