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1. 发明授权

US07838913B2 Hybrid FET incorporating a finFET and a planar FET 有权
标题翻译：并联有finFET和平面FET的混合FET
公开(公告)号：US07838913B2
公开(公告)日：2010-11-23
申请号：US12128134
申请日：2008-05-28
申请人： Kangguo Cheng , Qingqing Liang , Huilong Zhu
发明人： Kangguo Cheng , Qingqing Liang , Huilong Zhu
IPC分类号： H01L21/338
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L29/66795
摘要： A stack of a vertical fin and a planar semiconductor portion are formed on a buried insulator layer of a semiconductor-on-insulator substrate. A hybrid field effect transistor (FET) is formed which incorporates a finFET located on the vertical fin and a planar FET located on the planar semiconductor portion. The planar FET enables a continuous spectrum of on-current. The surfaces of the vertical fin and the planar semiconductor portion may be set to coincide with crystallographic orientations. Further, different crystallographic orientations may be selected for the surfaces of the vertical fin and the surfaces of the planar semiconductor portion to tailor the characteristics of the hybrid FET.
摘要翻译：在绝缘体上半导体衬底的掩埋绝缘体层上形成垂直鳍片和平面半导体部分的叠层。形成混合场效应晶体管（FET），其包含位于垂直鳍片上的finFET和位于平面半导体部分上的平面FET。平面FET使能连续的导通电流。可以将垂直翅片和平面半导体部分的表面设置为与结晶取向一致。此外，可以为垂直翅片的表面和平面半导体部分的表面选择不同的晶体取向以调整混合FET的特性。

2. 发明申请

US20090294800A1 HYBRID FET INCORPORATING A FINFET AND A PLANAR FET 有权
标题翻译：并入FinFET和平面FET的混合FET
公开(公告)号：US20090294800A1
公开(公告)日：2009-12-03
申请号：US12128134
申请日：2008-05-28
申请人： Kangguo Cheng , Qingqing Liang , Huilong Zhu
发明人： Kangguo Cheng , Qingqing Liang , Huilong Zhu
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L29/66795
摘要： A stack of a vertical fin and a planar semiconductor portion are formed on a buried insulator layer of a semiconductor-on-insulator substrate. A hybrid field effect transistor (FET) is formed which incorporates a finFET located on the vertical fin and a planar FET located on the planar semiconductor portion. The planar FET enables a continuous spectrum of on-current. The surfaces of the vertical fin and the planar semiconductor portion may be set to coincide with crystallographic orientations. Further, different crystallographic orientations may be selected for the surfaces of the vertical fin and the surfaces of the planar semiconductor portion to tailor the characteristics of the hybrid FET.
摘要翻译：在绝缘体上半导体衬底的掩埋绝缘体层上形成垂直鳍片和平面半导体部分的叠层。形成混合场效应晶体管（FET），其包含位于垂直鳍片上的finFET和位于平面半导体部分上的平面FET。平面FET使能连续的导通电流。可以将垂直翅片和平面半导体部分的表面设置为与结晶取向一致。此外，可以为垂直翅片的表面和平面半导体部分的表面选择不同的晶体取向以调整混合FET的特性。

3. 发明授权

US07776674B2 Hybrid strained orientated substrates and devices 失效
标题翻译：混合应变取向基板和器件
公开(公告)号：US07776674B2
公开(公告)日：2010-08-17
申请号：US12184614
申请日：2008-08-01
申请人： Kangguo Cheng , Huilong Zhu
发明人： Kangguo Cheng , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： A method for forming a semiconductor structure. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The method further includes forming a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials. The second semiconductor region has the first crystallographic orientation, whereas the fourth semiconductor region has the second crystallographic orientation.
摘要翻译：一种形成半导体结构的方法。该方法包括提供半导体结构，其包括（a）衬底，（b）在衬底顶部上的第一半导体区域，其中第一半导体区域包括与第一半导体区别的第一半导体材料和第二半导体材料材料，并且其中所述第一半导体区域具有第一晶体取向，以及（c）在所述衬底的顶部上的包括所述第一和第二半导体材料并具有第二晶体取向的第三半导体区域。该方法还包括分别在第一和第三半导体区域的顶部上形成第二半导体区域和第四半导体区域。第二和第四半导体区域都包括第一和第二半导体材料。第二半导体区域具有第一晶体取向，而第四半导体区域具有第二晶体取向。

4. 发明申请

US20080311708A1 HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES 失效
标题翻译：混合应变取向的基板和器件
公开(公告)号：US20080311708A1
公开(公告)日：2008-12-18
申请号：US12184614
申请日：2008-08-01
申请人： Kangguo Cheng , Huilong Zhu
发明人： Kangguo Cheng , Huilong Zhu
IPC分类号： H01L21/84
CPC分类号： H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： A method for forming a semiconductor structure. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The method further includes forming a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials. The second semiconductor region has the first crystallographic orientation, whereas the fourth semiconductor region has the second crystallographic orientation.
摘要翻译：一种形成半导体结构的方法。该方法包括提供半导体结构，其包括（a）衬底，（b）在衬底顶部上的第一半导体区域，其中第一半导体区域包括与第一半导体区别的第一半导体材料和第二半导体材料材料，并且其中所述第一半导体区域具有第一晶体取向，以及（c）在所述衬底的顶部上的包括所述第一和第二半导体材料并具有第二晶体取向的第三半导体区域。该方法还包括分别在第一和第三半导体区域的顶部上形成第二半导体区域和第四半导体区域。第二和第四半导体区域都包括第一和第二半导体材料。第二半导体区域具有第一晶体取向，而第四半导体区域具有第二晶体取向。

5. 发明申请

US20070267634A1 HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES 有权
标题翻译：混合应变取向的基板和器件
公开(公告)号：US20070267634A1
公开(公告)日：2007-11-22
申请号：US11419308
申请日：2006-05-19
申请人： Kangguo Cheng , Huilong Zhu
发明人： Kangguo Cheng , Huilong Zhu
IPC分类号： H01L29/00
CPC分类号： H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The method further includes forming a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials. The second semiconductor region has the first crystallographic orientation, whereas the fourth semiconductor region has the second crystallographic orientation.
摘要翻译：半导体结构及其形成方法。该方法包括提供半导体结构，其包括（a）衬底，（b）在衬底顶部上的第一半导体区域，其中第一半导体区域包括与第一半导体区别的第一半导体材料和第二半导体材料材料，并且其中所述第一半导体区域具有第一晶体取向，以及（c）在所述衬底的顶部上的包括所述第一和第二半导体材料并具有第二晶体取向的第三半导体区域。该方法还包括分别在第一和第三半导体区域的顶部上形成第二半导体区域和第四半导体区域。第二和第四半导体区域都包括第一和第二半导体材料。第二半导体区域具有第一晶体取向，而第四半导体区域具有第二晶体取向。

6. 发明申请

US20100283093A1 Structure and Method to Form EDRAM on SOI Substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20100283093A1
公开(公告)日：2010-11-11
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/10 , H01L21/02
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

7. 发明授权

US07436006B2 Hybrid strained orientated substrates and devices 有权
标题翻译：混合应变取向基板和器件
公开(公告)号：US07436006B2
公开(公告)日：2008-10-14
申请号：US11419308
申请日：2006-05-19
申请人： Kangguo Cheng , Huilong Zhu
发明人： Kangguo Cheng , Huilong Zhu
IPC分类号： H01L31/072 , H01L31/109
CPC分类号： H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The method further includes forming a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials. The second semiconductor region has the first crystallographic orientation, whereas the fourth semiconductor region has the second crystallographic orientation.
摘要翻译：半导体结构及其形成方法。该方法包括提供半导体结构，其包括（a）衬底，（b）在衬底顶部上的第一半导体区域，其中第一半导体区域包括与第一半导体区别的第一半导体材料和第二半导体材料材料，并且其中所述第一半导体区域具有第一晶体取向，以及（c）在所述衬底的顶部上的包括所述第一和第二半导体材料并具有第二晶体取向的第三半导体区域。该方法还包括分别在第一和第三半导体区域的顶部上形成第二半导体区域和第四半导体区域。第二和第四半导体区域都包括第一和第二半导体材料。第二半导体区域具有第一晶体取向，而第四半导体区域具有第二晶体取向。

8. 发明申请

US20080073669A1 STRUCTURE AND METHOD FOR MANUFACTURING HIGH PERFORMANCE AND LOW LEAKEAGE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：用于制造高性能和低照度场效应晶体管的结构和方法
公开(公告)号：US20080073669A1
公开(公告)日：2008-03-27
申请号：US11836393
申请日：2007-08-09
申请人： Huilong Zhu , Kangguo Cheng
发明人： Huilong Zhu , Kangguo Cheng
IPC分类号： H01L29/778
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/1054 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： There is provided a field effect transistor (FET) including a source side semiconductor; a drain side semiconductor; and a gate. The source side semiconductor is made of a high mobility semiconductor material, and the drain side semiconductor is made of a low leakage semiconductor material. In one embodiment, the FET is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). There is also provided a method for manufacturing the FET.
摘要翻译：提供了包括源极半导体的场效应晶体管（FET）; 漏极侧半导体; 和一个门。源极半导体由高迁移率半导体材料制成，漏极侧半导体由低泄漏半导体材料制成。在一个实施例中，FET是金属氧化物半导体场效应晶体管（MOSFET）。还提供了一种用于制造FET的方法。

9. 发明申请

US20070269963A1 STRAINED HOT (HYBRID ORIENTATION TECHNOLOGY) MOSFETs 有权
标题翻译：应变热（混合方向技术）MOSFET
公开(公告)号：US20070269963A1
公开(公告)日：2007-11-22
申请号：US11419312
申请日：2006-05-19
申请人： Kangguo Cheng , Woo-Hyeong Lee , Huilong Zhu
发明人： Kangguo Cheng , Woo-Hyeong Lee , Huilong Zhu
IPC分类号： H01L21/20
CPC分类号： H01L21/823878 , H01L21/187 , H01L21/2007 , H01L21/823807 , H01L21/84 , H01L29/045 , H01L29/1054 , H01L29/78
摘要： A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semiconductor layer on top of the buried oxide layer. The second semiconductor layer has a second crystallographic orientation different from the first crystallographic orientation. The method further includes forming a third semiconductor layer on top of the first semiconductor layer which has the first crystallographic orientation. The method further includes forming a fourth semiconductor layer on top of the third semiconductor layer. The fourth semiconductor layer (a) comprises a different material than that of the third semiconductor layer, and (b) has the first crystallographic orientation.
摘要翻译：应变HOT MOSFET制造方法。 MOSFET制造方法包括提供半导体结构，其包括：（a）具有第一晶体取向的第一半导体层，（b）在第一半导体层的顶部上的掩埋绝缘层，（c）第二半导体层，掩埋氧化层。第二半导体层具有不同于第一晶体取向的第二晶体取向。该方法还包括在具有第一晶体取向的第一半导体层的顶部上形成第三半导体层。该方法还包括在第三半导体层的顶部上形成第四半导体层。第四半导体层（a）包括与第三半导体层不同的材料，（b）具有第一晶体取向。

10. 发明申请

US20120171827A1 STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20120171827A1
公开(公告)日：2012-07-05
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

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