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    • 10. 发明授权
    • Transmitting apparatus with bit arrangement method
    • 带排列方式的发送装置
    • US07860186B2
    • 2010-12-28
    • US10899068
    • 2004-07-27
    • Tetsuya YanoKazuhisa ObuchiShunji Miyazaki
    • Tetsuya YanoKazuhisa ObuchiShunji Miyazaki
    • H04L27/36
    • H04L27/3488H03M13/25H03M13/2957H04L1/0041H04L1/0057H04L1/0067H04L1/16
    • A transmitting apparatus comprising circuitry operable to generate a plurality of bit sequences using bits included in a first data block and a second data block, circuitry operable to control the plurality of bit sequences to correspond to a signal point on the phase plane, comprising a bit sequence generating unit operable to control the generation of the bit sequences to adjust an occupation rate occupied with predetermined bits included in the first data block to be closer to an occupation rate occupied with predetermined bits included in the second data block in regard to bit positions of the predetermined bits, based on an error tolerance of the respective bit sequences generated resulting from the correspondence to a signal point on the phase plane, and circuitry operable to transmit the signals obtained by multi-level modulations in accordance with each signal point.
    • 一种发送装置,包括可操作以使用包括在第一数据块和第二数据块中的比特来生成多个比特序列的电路,所述电路可操作以控制所述多个比特序列以对应于所述相位平面上的信号点,包括比特 序列产生单元,其可操作以控制比特序列的生成,以调整占据第一数据块中包含的预定比特占有率的占有率,以使其相对于第二数据块中包含的预定比特占据的占用率更接近第 基于由与相位平面上的信号点的对应产生的相应比特序列的误差容限,以及可操作以根据每个信号点发送通过多电平调制获得的信号的电路。