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    • 1. 发明授权
    • Computer system for sharing I/O device
    • 用于共享I / O设备的计算机系统
    • US07890669B2
    • 2011-02-15
    • US11561557
    • 2006-11-20
    • Keitaro UeharaYuji TsushimaToshiomi MorikiYoshiko Yasuda
    • Keitaro UeharaYuji TsushimaToshiomi MorikiYoshiko Yasuda
    • G06F13/28
    • G06F13/385
    • Provided is a computer system in which an I/O card is shared among physical servers and logical servers. Servers are set in advance such that one I/O card is used exclusively by one physical or logical server, or shared among a plurality of servers. An I/O hub allocates a virtual MM I/O address unique to each physical or logical server to a physical MM I/O address associated with each I/O card. The I/O hub keeps allocation information indicating the relation between the allocated virtual MM I/O address, the physical MM I/O address, and a server identifier unique to each physical or logical server. When a request to access an I/O card is sent from a physical or logical server, the allocation information is referred to and a server identifier is extracted from the access request. The extracted server identifier is used to identify the physical or logical server that has made the access request.
    • 提供了在物理服务器和逻辑服务器之间共享I / O卡的计算机系统。 服务器预先设置,使得一个I / O卡由一个物理或逻辑服务器专门使用,或者在多个服务器之间共享。 I / O集线器将每个物理或逻辑服务器唯一的虚拟MM I / O地址分配给与每个I / O卡相关联的物理MM I / O地址。 I / O集线器保持指示分配的虚拟MM I / O地址,物理MM I / O地址与每个物理或逻辑服务器唯一的服务器标识之间的关系的分配信息。 当从物理或逻辑服务器发送访问I / O卡的请求时,参考分配信息并从访问请求中提取服务器标识符。 提取的服务器标识符用于标识已进行访问请求的物理或逻辑服务器。
    • 2. 发明申请
    • COMPUTER SYSTEM FOR SHARING I/O DEVICE
    • 用于共享I / O设备的计算机系统
    • US20070143395A1
    • 2007-06-21
    • US11561557
    • 2006-11-20
    • Keitaro UEHARAYuji TsushimaToshiomi MorikiYoshiko Yasuda
    • Keitaro UEHARAYuji TsushimaToshiomi MorikiYoshiko Yasuda
    • G06F15/16
    • G06F13/385
    • Provided is a computer system in which an I/O card is shared among physical servers and logical servers. Servers are set in advance such that one I/O card is used exclusively by one physical or logical server, or shared among a plurality of servers. An I/O hub allocates a virtual MM I/O address unique to each physical or logical server to a physical MM I/O address associated with each I/O card. The I/O hub keeps allocation information indicating the relation between the allocated virtual MM I/O address, the physical MM I/O address, and a server identifier unique to each physical or logical server. When a request to access an I/O card is sent from a physical or logical server, the allocation information is referred to and a server identifier is extracted from the access request. The extracted server identifier is used to identify the physical or logical server that has made the access request.
    • 提供了在物理服务器和逻辑服务器之间共享I / O卡的计算机系统。 服务器预先设置,使得一个I / O卡由一个物理或逻辑服务器专门使用,或者在多个服务器之间共享。 I / O集线器将每个物理或逻辑服务器唯一的虚拟MM I / O地址分配给与每个I / O卡相关联的物理MM I / O地址。 I / O集线器保持指示分配的虚拟MM I / O地址,物理MM I / O地址与每个物理或逻辑服务器唯一的服务器标识之间的关系的分配信息。 当从物理或逻辑服务器发送访问I / O卡的请求时,参考分配信息并从访问请求中提取服务器标识符。 提取的服务器标识符用于标识已进行访问请求的物理或逻辑服务器。
    • 3. 发明授权
    • Shared memory multiprocessor performing cache coherence control and node controller therefor
    • 共享内存多处理器执行高速缓存一致性控制和节点控制器
    • US06636926B2
    • 2003-10-21
    • US09740816
    • 2000-12-21
    • Yoshiko YasudaNaoki HamanakaToru ShonaiHideya AkashiYuji TsushimaKeitaro Uehara
    • Yoshiko YasudaNaoki HamanakaToru ShonaiHideya AkashiYuji TsushimaKeitaro Uehara
    • G06F1300
    • G06F12/0813G06F12/0833G06F2212/1016
    • Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.
    • 每个节点包括用于解码由处理器或I / O设备发出的访问请求的控制信息和地址信息的节点控制器,基于解码结果生成指示高速缓存一致性控制的高速缓存一致性控制信息 是否需要节点信息和传输目的地的单位信息,并将这些信息添加到访问请求。 用于连接节点控制器中的单元的节点内连接电路保持高速缓存一致性控制信息,节点信息和添加到访问请求的单元信息。 当高速缓存一致性控制信息指示不需要高速缓存一致性控制并且节点信息指示本地节点时,节点内连接电路不是将互连节点的节点间连接电路的访问请求传送到节点间连接电路,而是直接连接到 单位由单位信息指定。
    • 6. 发明授权
    • Shared memory multiprocessor performing cache coherence control and node controller therefor
    • 共享内存多处理器执行高速缓存一致性控制和节点控制器
    • US06874053B2
    • 2005-03-29
    • US10654983
    • 2003-09-05
    • Yoshiko YasudaNaoki HamanakaToru ShonaiHideya AkashiYuji TsushimaKeitaro Uehara
    • Yoshiko YasudaNaoki HamanakaToru ShonaiHideya AkashiYuji TsushimaKeitaro Uehara
    • G06F12/08G06F15/173G06F13/00G06F15/167
    • G06F12/0813G06F12/0833G06F2212/1016
    • Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit inter-connecting the node but directly to the unit designated by the unit information.
    • 每个节点包括用于解码由处理器或I / O设备发出的访问请求的控制信息和地址信息的节点控制器,基于解码结果生成指示高速缓存一致性控制的高速缓存一致性控制信息 是否需要节点信息和传输目的地的单位信息,并将这些信息添加到访问请求。 用于连接节点控制器中的单元的节点内连接电路保持高速缓存一致性控制信息,节点信息和添加到访问请求的单元信息。 当高速缓存一致性控制信息指示不需要高速缓存一致性控制并且节点信息指示本地节点时,节点间连接电路将访问请求传送到不是直接连接节点的节点间连接电路 到由单位信息指定的单位。