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1. 发明授权

US08685627B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US08685627B2
公开(公告)日：2014-04-01
申请号：US12266459
申请日：2008-11-06
申请人： Ki Lyoung Lee , Cheol Kyu Bok , Keum Do Ban , Jung Gun Heo
发明人： Ki Lyoung Lee , Cheol Kyu Bok , Keum Do Ban , Jung Gun Heo
IPC分类号： H01L21/02
CPC分类号： H01L21/308 , H01L21/0337
摘要： A method for manufacturing a semiconductor device includes forming an etch-target layer over a semiconductor substrate having a lower structure, forming a first mask pattern over the etch-target layer, forming a spacer material layer with a uniform thickness over the etch-target layer including the first mask pattern, forming a second mask pattern on an indented region of the space material layer, and etching the etch-target layer with the first mask pattern and the second mask pattern as an etch mask to form a fine pattern.
摘要翻译：一种用于制造半导体器件的方法包括在具有较低结构的半导体衬底上形成蚀刻目标层，在蚀刻靶层上形成第一掩模图案，在蚀刻靶层上形成均匀厚度的间隔物材料层包括第一掩模图案，在空间材料层的凹陷区域上形成第二掩模图案，并且用第一掩模图案和第二掩模图案蚀刻蚀刻目标层作为蚀刻掩模以形成精细图案。

2. 发明授权

US07994050B2 Method for forming dual damascene pattern 有权
标题翻译：形成双镶嵌图案的方法
公开(公告)号：US07994050B2
公开(公告)日：2011-08-09
申请号：US12804150
申请日：2010-07-15
申请人： Ki Lyoung Lee , Jung Gun Heo
发明人： Ki Lyoung Lee , Jung Gun Heo
IPC分类号： H01L21/768
CPC分类号： H01L21/76808 , G03F7/091 , H01L21/0276 , H01L21/31144
摘要： A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole.
摘要翻译：形成双镶嵌图案的方法包括制备包括硅树脂作为基础树脂的多功能硬掩模组合物，其中所述硅树脂占树脂总重量的约20至45重量％的硅分子; 通过在硬接线层上依次形成自配置接触（SAC）绝缘膜，第一电介质膜，蚀刻阻挡膜和第二电介质膜来形成沉积结构; 蚀刻沉积结构以暴露硬接线层，从而形成通孔; 在第二电介质膜上和通孔中涂覆多功能硬掩模组合物以形成多功能硬掩模膜; 并蚀刻所得到的结构，以使用光致抗蚀剂图案作为蚀刻掩模使第一电介质膜的一部分露出，从而形成宽度大于通孔的宽度的沟槽。

3. 发明申请

US20100311239A1 Method for forming dual damascene pattern 有权
标题翻译：形成双镶嵌图案的方法
公开(公告)号：US20100311239A1
公开(公告)日：2010-12-09
申请号：US12804150
申请日：2010-07-15
申请人： Ki Lyoung Lee , Jung Gun Heo
发明人： Ki Lyoung Lee , Jung Gun Heo
IPC分类号： H01L21/768
CPC分类号： H01L21/76808 , G03F7/091 , H01L21/0276 , H01L21/31144
摘要： A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole.
摘要翻译：形成双镶嵌图案的方法包括制备包括硅树脂作为基础树脂的多功能硬掩模组合物，其中所述硅树脂占树脂总重量的约20至45重量％的硅分子; 通过在硬接线层上依次形成自配置接触（SAC）绝缘膜，第一电介质膜，蚀刻阻挡膜和第二电介质膜来形成沉积结构; 蚀刻沉积结构以暴露硬接线层，从而形成通孔; 在第二电介质膜上和通孔中涂覆多功能硬掩模组合物以形成多功能硬掩模膜; 并蚀刻所得到的结构，以使用光致抗蚀剂图案作为蚀刻掩模使第一电介质膜的一部分露出，从而形成宽度大于通孔的宽度的沟槽。

4. 发明授权

US07811929B2 Method for forming dual damascene pattern 有权
标题翻译：形成双镶嵌图案的方法
公开(公告)号：US07811929B2
公开(公告)日：2010-10-12
申请号：US11812910
申请日：2007-06-22
申请人： Ki Lyoung Lee , Jung Gun Heo
发明人： Ki Lyoung Lee , Jung Gun Heo
IPC分类号： H01L21/768
CPC分类号： H01L21/76808 , G03F7/091 , H01L21/0276 , H01L21/31144
摘要： A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin; forming a deposition structure including a self-arrangement contact insulation film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; forming the multi-functional hard mask composition on the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film, thereby forming a trench having a width wider than that of the via hole; and removing the multi-functional hard mask film.
摘要翻译：形成双镶嵌图案的方法包括制备包括硅树脂作为基础树脂的多功能硬掩模组合物; 在硬接线层上形成包括自配置接触绝缘膜，第一电介质膜，蚀刻阻挡膜和第二电介质膜的沉积结构; 蚀刻沉积结构以暴露硬接线层，从而形成通孔; 在第二电介质膜和通孔中形成多功能硬掩模组合物以形成多功能硬掩模膜; 并蚀刻所得到的结构以暴露第一电介质膜的一部分，从而形成宽度大于通孔的宽度的沟槽; 并去除多功能硬掩模膜。

5. 发明申请

US20080268641A1 Method for forming dual damascene pattern 有权
标题翻译：形成双镶嵌图案的方法
公开(公告)号：US20080268641A1
公开(公告)日：2008-10-30
申请号：US11812910
申请日：2007-06-22
申请人： Ki Lyoung Lee , Jung Gun Heo
发明人： Ki Lyoung Lee , Jung Gun Heo
IPC分类号： H01L21/768 , H01L21/3065
CPC分类号： H01L21/76808 , G03F7/091 , H01L21/0276 , H01L21/31144
摘要： A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin; forming a deposition. structure including a self-arrangement contact insulation film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; forming the multi-functional hard mask composition on the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film, thereby forming a trench having a width wider than that of the via hole; and removing the multi-functional hard mask film.
摘要翻译：形成双镶嵌图案的方法包括制备包括硅树脂作为基础树脂的多功能硬掩模组合物; 形成沉积物。包括自配置接触绝缘膜，第一电介质膜，蚀刻阻挡膜和在硬接线层上的第二电介质膜的结构; 蚀刻沉积结构以暴露硬接线层，从而形成通孔; 在第二电介质膜和通孔中形成多功能硬掩模组合物以形成多功能硬掩模膜; 并蚀刻所得到的结构以暴露第一电介质膜的一部分，从而形成宽度大于通孔的宽度的沟槽; 并去除多功能硬掩模膜。

6. 发明授权

US08389400B2 Method of manufacturing fine patterns of semiconductor device 有权
标题翻译：制造半导体器件精细图案的方法
公开(公告)号：US08389400B2
公开(公告)日：2013-03-05
申请号：US12650222
申请日：2009-12-30
申请人： Ki Lyoung Lee , Sa Ro Han Park
发明人： Ki Lyoung Lee , Sa Ro Han Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/0337
摘要： A method of forming fine patterns of a semiconductor device comprises forming sacrificial film patterns of a line type in a cell region of a semiconductor substrate and, at the same time, forming pad patterns in a peripheral region of the semiconductor substrate, forming a spacer on sidewalls of each of the sacrificial film patterns and the pad patterns, forming a gap-fill layer on sidewalls of the spacers to thereby form line and space patterns, including the sacrificial film patterns and the gap-fill layers, in the cell region, and separating the line and space patterns of the cell region at regular intervals and, at the same time, etching the pad patterns of the peripheral region to thereby form specific patterns in the peripheral region.
摘要翻译：形成半导体器件的精细图案的方法包括在半导体衬底的单元区域中形成线型的牺牲膜图案，并且同时在半导体衬底的周边区域中形成衬垫图案，形成间隔物每个牺牲膜图案和焊盘图案的侧壁，在间隔物的侧壁上形成间隙填充层，从而在单元区域中形成包括牺牲膜图案和间隙填充层的线和间隔图案，以及以规则的间隔分离单元区域的线和空间图案，并且同时蚀刻周边区域的焊盘图案，从而在周边区域中形成特定图案。

7. 发明授权

US08304174B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08304174B2
公开(公告)日：2012-11-06
申请号：US12164071
申请日：2008-06-29
申请人： Ki Lyoung Lee , Cheol Kyu Bok
发明人： Ki Lyoung Lee , Cheol Kyu Bok
IPC分类号： G03F7/20
CPC分类号： H01L21/0337 , H01L21/28273 , H01L27/11521 , H01L27/11524
摘要： A method for fabricating a semiconductor device includes forming a first mask pattern over an etch target layer, forming a second mask pattern over the etch target layer, forming spacers at sidewalls of the first mask pattern and the second mask pattern, and etching the etch target layer with an etching mask where the second mask pattern is removed. The method improves a profile of a pad pattern and critical dimension uniformity.
摘要翻译：一种用于制造半导体器件的方法包括在蚀刻目标层上形成第一掩模图案，在蚀刻目标层上形成第二掩模图案，在第一掩模图案和第二掩模图案的侧壁处形成间隔物，并蚀刻蚀刻靶层，其中除去第二掩模图案的蚀刻掩模。该方法改善了焊盘图案的轮廓和临界尺寸均匀性。

8. 发明授权

US07989145B2 Method for forming fine pattern of semiconductor device 失效
标题翻译：用于形成半导体器件精细图案的方法
公开(公告)号：US07989145B2
公开(公告)日：2011-08-02
申请号：US11964693
申请日：2007-12-26
申请人： Ki Lyoung Lee , Cheol Kyu Bok
发明人： Ki Lyoung Lee , Cheol Kyu Bok
IPC分类号： G03F7/26
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/0273 , H01L21/0338 , H01L21/31144
摘要： A method for forming a fine pattern of a semiconductor device comprises forming a spin-on-carbon layer over an underlying layer, forming an anti-reflection pattern including a silicon containing polymer with a first etching mask pattern, forming a photoresist pattern including a silicon containing polymer with a second etching mask pattern between elements of the first etching mask pattern, and etching the spin-on-carbon layer with the etching mask patterns to reduce the process steps and the manufacturing cost, thereby obtaining a uniform pattern profile.
摘要翻译：用于形成半导体器件的精细图案的方法包括在下层上形成自旋碳层，用第一蚀刻掩模图形成包含含硅聚合物的抗反射图案，形成包括硅的光致抗蚀剂图案在第一蚀刻掩模图案的元件之间具有第二蚀刻掩模图案，并用蚀刻掩模图案蚀刻自旋碳层，以减少工艺步骤和制造成本，从而获得均匀的图案轮廓。

9. 发明申请

US20080009138A1 METHOD FOR FORMING PATTERN OF A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体器件图案的方法
公开(公告)号：US20080009138A1
公开(公告)日：2008-01-10
申请号：US11739651
申请日：2007-04-24
申请人： Ki Lyoung Lee
发明人： Ki Lyoung Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338
摘要： A method for forming a pattern of a semiconductor device comprises sequentially forming a carbon-rich polymer, an antireflection film containing silicon, and a photoresist film over a semiconductor substrate. A double patterning process is then performed. The double patterning process may be a negative tone double patterning process or a positive tone double patterning process.
摘要翻译：用于形成半导体器件的图案的方法包括在半导体衬底上依次形成富含碳的聚合物，含硅的抗反射膜和光致抗蚀剂膜。然后进行双重图案化处理。双重图案化工艺可以是负色调双重图案化工艺或正色调双重图案化工艺。

10. 发明授权

US08129094B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US08129094B2
公开(公告)日：2012-03-06
申请号：US12163836
申请日：2008-06-27
申请人： Ki Lyoung Lee
发明人： Ki Lyoung Lee
IPC分类号： G03F7/26
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139
摘要： A spacer is formed on side and top portions of a photoresist pattern after a mask process is performed so that the spacer may be used as an etching mask. The spacer is formed using a polymer deposition layer which is a low temperature oxide or nitride that can be deposited on side and top portions of the photoresist pattern at 75˜220° C. after the mask process is performed. A method for manufacturing a semiconductor device includes forming a bottom anti-reflection coating film on an etch-target layer, patterning a photoresist layer formed on the bottom anti-reflection coating film, forming an insulation layer on a patterned photoresist layer and the bottom anti-reflection coating film, etching back the insulation layer to form a spacer on sidewalls of the patterned photoresist layer, and etching the bottom anti-reflection coating film and the etching target layer exposed by the spacer to form a fine pattern.
摘要翻译：在执行掩模处理之后，在光致抗蚀剂图案的侧部和顶部上形成间隔物，使得间隔物可以用作蚀刻掩模。间隔物是使用聚合物沉积层形成的，该聚合物沉积层是在进行掩模处理之后可以在75〜220℃下沉积在光刻胶图案的侧面和顶部的低温氧化物或氮化物。一种制造半导体器件的方法包括在蚀刻目标层上形成底部防反射涂膜，对形成在底部抗反射涂膜上的光刻胶层进行构图，在图案化的光致抗蚀剂层上形成绝缘层，对反射涂膜进行蚀刻，在图案化的光致抗蚀剂层的侧壁上蚀刻隔离层，并蚀刻由间隔物露出的底部防反射涂膜和蚀刻目标层，形成精细图案。

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