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1. 发明授权

US09648483B2 Discovery method and apparatuses and system for discovery 有权
公开(公告)号：US09648483B2
公开(公告)日：2017-05-09
申请号：US14415559
申请日：2012-08-28
申请人： Kimmo Kuusilinna , Timo Aaltonen , Tapani Leppänen , Arto Palin
发明人： Kimmo Kuusilinna , Timo Aaltonen , Tapani Leppänen , Arto Palin
IPC分类号： H04L12/28 , G06F15/173 , H04Q5/22 , H04W8/00 , H04W52/02 , H04W76/02 , H04W84/12
CPC分类号： H04W8/005 , H04W52/0209 , H04W52/0261 , H04W76/14 , H04W84/12 , Y02D70/142 , Y02D70/144 , Y02D70/164 , Y02D70/166
摘要： The invention relates to methods, apparatuses, systems and computer program products for discovery of nearby devices (510, 520, 525, 540, 545). To facilitate discovery of nearby, i.e. proximal, devices, a discovery control signal (570, 572, 574, 576, 578) from a control device (530) may be used to control the discovery, e.g. how or when the discovery is carried out. The devices may send status information of their status to be used by the control device or the control system for forming the discovery control signal. The control device, e.g. a server, may form the discovery control signal based on this status information. Discovery of proximal devices may then be carried out based on the received discovery control signal.

2. 发明申请

US20150208226A1 DISCOVERY METHOD AND APPARATUSES AND SYSTEM FOR DISCOVERY 审中-公开
标题翻译：发现方法和发现的方法和系统
公开(公告)号：US20150208226A1
公开(公告)日：2015-07-23
申请号：US14419594
申请日：2012-08-28
申请人： Kimmo Kuusilinna , Timo Aaltonen , Tapani Leppänen
发明人： Kimmo Kuusilinna , Timo Aaltonen , Tapani Leppänen
IPC分类号： H04W8/00 , H04W40/24 , H04W64/00 , H04W4/02
CPC分类号： H04W8/005 , H04W4/023 , H04W4/029 , H04W4/21 , H04W8/22 , H04W40/246 , H04W64/003 , H04W84/18
摘要： The invention relates to methods, apparatuses, systems and computer program products for discovery of nearby devices. To facilitate discovery of nearby, i.e. proximal, devices, after receiving a trigger signal (110), that is, a signal related to a user action, proximity of other devices is determined and a proximity fingerprint is formed from this information (120), for example to be stored in a fingerprint database (130). When a change in proximity information of a device is detected, proximity fingerprints are accessed and the fingerprints are searched for in the current proximity information of the user device. In this manner, the user may be alerted or programs (or the system) may be controlled when a stored proximity fingerprint is detected in the current set of nearby devices.
摘要翻译：本发明涉及用于发现附近装置的方法，装置，系统和计算机程序产品。为了便于发现附近的设备，即在接收到触发信号（110）之后，即与用户动作有关的信号，确定其他设备的接近度，并且从该信息（120）形成接近指纹，例如存储在指纹数据库（130）中。当检测到设备的邻近信息的改变时，接近指纹被访问，并且在用户设备的当前邻近信息中搜索指纹。以这种方式，当在当前的一组附近设备中检测到存储的接近指纹时，可以警告用户或程序（或系统）。

3. 发明授权

US07717569B2 Projector screen with one or more markers 失效
标题翻译：具有一个或多个标记的投影机屏幕
公开(公告)号：US07717569B2
公开(公告)日：2010-05-18
申请号：US11404379
申请日：2006-04-13
申请人： Tomi Sokeila , Tapani Leppänen , Mika Pesonen , Kimmo Kuusilinna , Aki Launiainen
发明人： Tomi Sokeila , Tapani Leppänen , Mika Pesonen , Kimmo Kuusilinna , Aki Launiainen
IPC分类号： G03B21/14 , G03B21/56 , G03B21/58
CPC分类号： H04N9/3185 , G03B21/26
摘要： A projector screen includes one or more markers that are configured to be usable by projection processing circuitry in order to calculate a user perceived distortion in an image to be projected on the projector screen.
摘要翻译：投影仪屏幕包括被配置为可被投影处理电路使用的一个或多个标记，以便计算要投影在投影仪屏幕上的图像中的用户感知到的失真。

4. 发明申请

US20110197031A1 Update Handler For Multi-Channel Cache 审中-公开
标题翻译：多通道缓存更新处理程序
公开(公告)号：US20110197031A1
公开(公告)日：2011-08-11
申请号：US12701067
申请日：2010-02-05
申请人： Eero Aho , Jari Nikara , Kimmo Kuusilinna
发明人： Eero Aho , Jari Nikara , Kimmo Kuusilinna
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0844 , G06F12/084 , G06F12/0846 , G06F12/0851 , G06F12/0859 , G06F12/0862 , G06F2212/1016 , G06F2212/601 , G06F2212/6042
摘要： Disclosed herein is a miss handler for a multi-channel cache memory, and a method that includes determining a need to update a multi-channel cache memory due at least to one of an occurrence of a cache miss or a data prefetch being needed. The method further includes operating a multi-channel cache miss handler to update at least one cache channel storage of the multi-channel cache memory from a main memory.
摘要翻译：本文公开了一种用于多通道高速缓冲存储器的未命中处理器，以及一种方法，其包括至少由于存在高速缓存未命中的发生或需要的数据预取而导致更新多通道高速缓冲存储器的需要。该方法还包括操作多通道高速缓存未命中处理程序以从主存储器更新多通道高速缓冲存储器的至少一个高速缓存通道存储器。

5. 发明授权

US07894229B2 3D chip arrangement including memory manager 有权
标题翻译： 3D芯片布置包括内存管理器
公开(公告)号：US07894229B2
公开(公告)日：2011-02-22
申请号：US12343223
申请日：2008-12-23
申请人： Vesa Lahtinen , Tapio Hill , Kimmo Kuusilinna , Jari Nikara , Mika Kuulusa , Tommi Makelainen
发明人： Vesa Lahtinen , Tapio Hill , Kimmo Kuusilinna , Jari Nikara , Mika Kuulusa , Tommi Makelainen
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/02 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.
摘要翻译：涉及集中式存储器管理的系统，装置和方法能够动态分配和分配所有子系统的存储器。一个实施例涉及基底基板，基底基板上的逻辑管芯，并具有子系统，具有存储器模块的存储管芯，存储器管理单元，第一数据接口，其将具有所述至少一个逻辑管芯的存储器管理单元，将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口，将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口，其中所述配置接口包括面面对连接，将存储器管理单元与至少一个逻辑管芯连接的控制接口，其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上，并且存储器管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问，并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块一个配置界面。

6. 发明申请

US20100231286A1 Thermal Sensors For Stacked Dies 有权
标题翻译：热敏传感器用于堆叠模具
公开(公告)号：US20100231286A1
公开(公告)日：2010-09-16
申请号：US12306450
申请日：2007-12-24
申请人： Kimmo Kuusilinna , Jani Klint , Tapio Hill
发明人： Kimmo Kuusilinna , Jani Klint , Tapio Hill
IPC分类号： G01K7/00 , H01L25/04
CPC分类号： G01K7/425 , G01K2213/00 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06589 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to a method for obtaining temperature values from at least two thermal sensors arranged on resources within a three-dimensional die structure determining at least a partial three-dimensional temperature distribution for said die structure and controlling activity of said resources of said dies in response to said three-dimensional temperature distribution.
摘要翻译：本发明涉及一种用于从至少两个热传感器获得温度值的方法，所述温度传感器布置在三维模具结构内的资源上，确定所述模具结构的至少部分三维温度分布，并且控制所述模具的所述资源的活动对所述三维温度分布的响应。

7. 发明授权

US07477535B2 3D chip arrangement including memory manager 有权
标题翻译： 3D芯片布置包括内存管理器
公开(公告)号：US07477535B2
公开(公告)日：2009-01-13
申请号：US11543351
申请日：2006-10-05
申请人： Vesa Lahtinen , Tapio Hill , Kimmo Kuusilinna , Jari Nikara , Mika Kuulusa , Tommi Makelainen
发明人： Vesa Lahtinen , Tapio Hill , Kimmo Kuusilinna , Jari Nikara , Mika Kuulusa , Tommi Makelainen
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/02 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.
摘要翻译：涉及集中式存储器管理的系统，装置和方法能够动态分配和分配所有子系统的存储器。一个实施例涉及基底基板，基底基板上的逻辑管芯，并具有子系统，具有存储器模块的存储管芯，存储器管理单元，第一数据接口，其将具有所述至少一个逻辑管芯的存储器管理单元，将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口，将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口，其中所述配置接口包括面面对连接，将存储器管理单元与至少一个逻辑管芯连接的控制接口，其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上，并且存储器管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问，并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块一个配置界面。

8. 发明授权

US09892047B2 Multi-channel cache memory 有权
公开(公告)号：US09892047B2
公开(公告)日：2018-02-13
申请号：US13496649
申请日：2009-09-17
申请人： Jari Nikara , Eero Aho , Kimmo Kuusilinna
发明人： Jari Nikara , Eero Aho , Kimmo Kuusilinna
IPC分类号： G06F12/0842 , G06F12/08 , G06F12/0846 , G06F12/084 , G06F12/0844
CPC分类号： G06F12/0846 , G06F12/084 , G06F12/0842 , G06F12/0844
摘要： A cache memory including: a plurality of parallel input ports configured to receive, in parallel, memory access requests wherein each parallel input port is operable to receive a memory access request for any one of a plurality of processing units; and a plurality of cache blocks wherein each cache block is configured to receive memory access requests from a unique one of the plurality of input ports such that there is a one-to-one mapping between the plurality of parallel input ports and the plurality of cache blocks and wherein each of the plurality of cache blocks is configured to serve a unique portion of an address space of the memory.

9. 发明申请

US20090055639A1 Methods and system for modular device booting 审中-公开
标题翻译：模块化设备引导的方法和系统
公开(公告)号：US20090055639A1
公开(公告)日：2009-02-26
申请号：US11894122
申请日：2007-08-20
申请人： Kimmo Kuusilinna , Jari Nikara , Vesa Lahtinen , Antti Latva-Aho
发明人： Kimmo Kuusilinna , Jari Nikara , Vesa Lahtinen , Antti Latva-Aho
IPC分类号： G06F9/00
CPC分类号： G06F9/4416 , G06F9/4401
摘要： The present invention a method for modular device booting comprising retrieving a first boot code from a non-volatile memory element, receiving a memory access request from at least one subsystem, said memory access including at least a boot status indication indicating a memory region and a memory address, if said received address and region match a predefined address and region, associating said at least one subsystem with a corresponding subsystem boot code address included in said retrieved first boot code, retrieving a corresponding subsystem boot code from said associated boot code address, and transferring said boot code to said corresponding subsystem.
摘要翻译：本发明提供了一种用于模块化设备启动的方法，包括从非易失性存储器元件检索第一引导代码，从至少一个子系统接收存储器访问请求，所述存储器访问至少包括指示存储器区域的引导状态指示和存储器地址，如果所述接收到的地址和区域匹配预定义的地址和区域，则将所述至少一个子系统与包括在所述检索到的第一引导代码中的对应子系统引导代码地址相关联，从所述相关联的引导代码地址检索相应的子系统引导代码，以及将所述引导代码传送到所述对应的子系统。

10. 发明申请

US20080084725A1 3D chip arrangement including memory manager 有权
标题翻译： 3D芯片布置包括内存管理器
公开(公告)号：US20080084725A1
公开(公告)日：2008-04-10
申请号：US11543351
申请日：2006-10-05
申请人： Vesa Lahtinen , Tapio Hill , Kimmo Kuusilinna , Jari Nikara , Mika Kuulusa , Tommi Makelainen
发明人： Vesa Lahtinen , Tapio Hill , Kimmo Kuusilinna , Jari Nikara , Mika Kuulusa , Tommi Makelainen
IPC分类号： G11C5/02 , G06F15/177 , G06F9/24 , G06F9/00
CPC分类号： G11C5/025 , G11C5/02 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.
摘要翻译：涉及集中式存储器管理的系统，装置和方法能够动态分配和分配所有子系统的存储器。一个实施例涉及基底基板，基底基板上的逻辑管芯，并具有子系统，具有存储器模块的存储管芯，存储器管理单元，第一数据接口，其将具有所述至少一个逻辑管芯的存储器管理单元，将所述存储器管理单元与所述至少一个存储管芯连接的第二数据接口，将所述存储器管理单元与所述至少一个存储器管芯连接的配置接口，其中所述配置接口包括面面对连接，将存储器管理单元与至少一个逻辑管芯连接的控制接口，其中存储器管芯和逻辑管芯以堆叠配置布置在基底衬底上，并且存储器管理单元适于通过经由所述控制接口协商与所述子系统的允许的存储器访问来管理来自所述子系统的存储器访问，并且根据所述允许的存储器访问vi来配置所述至少一个存储器模块一个配置界面。

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