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1. 发明授权

US07355873B2 Highly integrated ternary semiconductor memory device 有权
标题翻译：高度集成的三元半导体存储器件
公开(公告)号：US07355873B2
公开(公告)日：2008-04-08
申请号：US11480908
申请日：2006-07-06
申请人： Koji Nii , Hideaki Abe , Kazunari Inoue
发明人： Koji Nii , Hideaki Abe , Kazunari Inoue
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory cells arranged in rows and columns. Each of the plurality of memory cells further includes a first cell storing one bit of said storage data, and a logical operation cell determining whether or not said search data and storage data match. A gate of a transistor forming each of a plurality of memory cells extends along the direction of said rows. Each of a plurality of wells in the region where the memory array is formed is formed so as to continue to a corresponding well of an adjacent memory cell in the direction of said columns.
摘要翻译： TCAM（三元内容可寻址存储器）单元阵列设置有搜索输入节点，其中输入一个比特的搜索数据;多个数据输入节点，其中输入与搜索数据的一个比特相对应的比特，并且多个的存储单元排列成行和列。多个存储单元中的每一个还包括存储所述存储数据的一位的第一单元和确定所述搜索数据和存储数据是否匹配的逻辑运算单元。形成多个存储单元的晶体管的栅极沿着所述行的方向延伸。形成存储器阵列的区域中的多个阱中的每一个形成为在所述列的方向上连续到相邻存储单元的相应阱。

2. 发明申请

US20070008760A1 Highly integrated ternary semiconductor memory device 有权
标题翻译：高度集成的三元半导体存储器件
公开(公告)号：US20070008760A1
公开(公告)日：2007-01-11
申请号：US11480908
申请日：2006-07-06
申请人： Koji Nii , Hideaki Abe , Kazunari Inoue
发明人： Koji Nii , Hideaki Abe , Kazunari Inoue
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory cells arranged in rows and columns. Each of the plurality of memory cells further includes a first cell storing one bit of said storage data, and a logical operation cell determining whether or not said search data and storage data match. A gate of a transistor forming each of a plurality of memory cells extends along the direction of said rows. Each of a plurality of wells in the region where the memory array is formed is formed so as to continue to a corresponding well of an adjacent memory cell in the direction of said columns.
摘要翻译： TCAM（三元内容可寻址存储器）单元阵列设置有搜索输入节点，其中输入一个比特的搜索数据;多个数据输入节点，其中输入与搜索数据的一个比特相对应的比特，并且多个的存储单元排列成行和列。多个存储单元中的每一个还包括存储所述存储数据的一位的第一单元和确定所述搜索数据和存储数据是否匹配的逻辑运算单元。形成多个存储单元的晶体管的栅极沿着所述行的方向延伸。形成存储器阵列的区域中的多个阱中的每一个形成为在所述列的方向上连续到相邻存储单元的相应阱。

3. 发明授权

US08441843B2 Semiconductor integrated circuit device 有权
公开(公告)号：US08441843B2
公开(公告)日：2013-05-14
申请号：US13317846
申请日：2011-10-31
申请人： Noriaki Maeda , Yoshihiro Shinozaki , Masanao Yamaoka , Yasuhisa Shimazaki , Masanori Isoda , Koji Nii
发明人： Noriaki Maeda , Yoshihiro Shinozaki , Masanao Yamaoka , Yasuhisa Shimazaki , Masanori Isoda , Koji Nii
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C5/063 , G11C5/14 , G11C11/419 , H01L27/11 , H01L27/1104
摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

4. 发明授权

US08363456B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08363456B2
公开(公告)日：2013-01-29
申请号：US12975400
申请日：2010-12-22
申请人： Koji Nii
发明人： Koji Nii
IPC分类号： G11C11/00
CPC分类号： G11C11/4125
摘要： To improve reliability of a semiconductor device having an SRAM.The semiconductor device has a memory cell including six n-channel type transistors and two p-channel type transistors formed over a silicon substrate. Over the silicon substrate, a first p well, a first n well, a second p well, a second n well, and a third p well are arranged in this order when viewed in a row direction. First and second positive-phase access transistors are disposed in the first p well, first and second driver transistors are disposed in the second p well, and first and second negative-phase access transistors are arranged in the third p well.
摘要翻译：为了提高具有SRAM的半导体器件的可靠性。半导体器件具有包括六个n沟道型晶体管和形成在硅衬底上的两个p沟道型晶体管的存储单元。在硅衬底上，当沿行方向观察时，以该顺序布置第一p阱，第一n阱，第二p阱，第二n阱和第三p阱。第一和第二正相存取晶体管设置在第一p阱中，第一和第二驱动晶体管设置在第二p阱中，第一和第二负相存取晶体管被布置在第三p阱中。

5. 发明授权

US08310883B2 Semiconductor memory device comprising a plurality of static memory cells 有权
标题翻译：半导体存储器件包括多个静态存储单元
公开(公告)号：US08310883B2
公开(公告)日：2012-11-13
申请号：US13193258
申请日：2011-07-28
申请人： Makoto Yabuuchi , Koji Nii
发明人： Makoto Yabuuchi , Koji Nii
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.
摘要翻译：降低电源电压的驱动器电源电路被布置在字线驱动器的电源节点处。驱动器电源电路包括N +掺杂多晶硅的非硅化物电阻元件和降低驱动器电源节点的电压电平的下拉电路。下拉电路包括具有与下拉驱动器电源节点的电压电平的存储单元晶体管相同的阈值电压特性的下拉晶体管，以及至少调节下拉电路的栅极电压的栅极控制电路晶体管。栅极控制电路以与存储单元晶体管的阈值电压的变化相关联的方式校正下拉晶体管的栅极电位。

6. 发明授权

US08072799B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08072799B2
公开(公告)日：2011-12-06
申请号：US12662029
申请日：2010-03-29
申请人： Noriaki Maeda , Yoshihiro Shinozaki , Masanao Yamaoka , Yasuhisa Shimazaki , Masanori Isoda , Koji Nii
发明人： Noriaki Maeda , Yoshihiro Shinozaki , Masanao Yamaoka , Yasuhisa Shimazaki , Masanori Isoda , Koji Nii
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C5/063 , G11C5/14 , G11C11/419 , H01L27/11 , H01L27/1104
摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.
摘要翻译：本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

7. 发明授权

US07876625B2 Semiconductor memory device comprising a plurality of static memory cells 有权
公开(公告)号：US07876625B2
公开(公告)日：2011-01-25
申请号：US12555447
申请日：2009-09-08
申请人： Makoto Yabuuchi , Koji Nii
发明人： Makoto Yabuuchi , Koji Nii
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

8. 发明授权

US07599214B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07599214B2
公开(公告)日：2009-10-06
申请号：US12325820
申请日：2008-12-01
申请人： Koji Nii
发明人： Koji Nii
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C5/14 , H01L27/11 , H01L27/1104
摘要： Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting the source voltage of driver transistors can be provided for each column, and the source voltage of driver transistors can be adjusted also in units of memory cell columns in the structure of single port memory cell.
摘要翻译：驱动晶体管的源触点通过使用存储单元内的内部金属线短路。该金属线与相邻列中的存储单元隔离，并以Z字形形式沿着存储单元列的方向延伸。可以为每列提供用于传输驱动晶体管的源电压的单独线路，并且也可以以单端口存储器单元的结构中的存储单元列为单位来调节驱动晶体管的源极电压。

9. 发明授权

US07570540B2 Multiport semiconductor memory device 失效
标题翻译：多端口半导体存储器件
公开(公告)号：US07570540B2
公开(公告)日：2009-08-04
申请号：US12219350
申请日：2008-07-21
申请人： Koji Nii
发明人： Koji Nii
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/16 , G11C11/413
摘要： In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD-Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports PA and PB simultaneously access the same row, the voltage level of word lines WLA, WLB is set to power supply voltage VDD-Vtp. Thus, a driving current amount of a memory cell is reduced, thereby preventing a reduction in a current ratio of a transistor. As a result, deterioration of SNM can be prevented.
摘要翻译：在同一行访问中，字线WLA和WLB的电压电平被设置为电源电压VDD-Vtp。另一方面，在不同的行访问中，字线WLA或WLB的电压电平被设置为电源电压VDD。因此，当两个端口PA和PB同时访问同一行时，字线WLA，WLB的电压电平被设置为电源电压VDD-Vtp。因此，减小了存储单元的驱动电流量，从而防止了晶体管的电流比的降低。结果，可以防止SNM的劣化。

10. 发明授权

US07477537B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07477537B2
公开(公告)日：2009-01-13
申请号：US11504079
申请日：2006-08-15
申请人： Noriaki Maeda , Yoshihiro Shinozaki , Masanao Yamaoka , Yasuhisa Shimazaki , Masanori Isoda , Koji Nii
发明人： Noriaki Maeda , Yoshihiro Shinozaki , Masanao Yamaoka , Yasuhisa Shimazaki , Masanori Isoda , Koji Nii
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C5/063 , G11C5/14 , G11C11/419 , H01L27/11 , H01L27/1104
摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.
摘要翻译：本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

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