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1. 发明授权

US08190968B2 Semiconductor memory device and data error detection and correction method of the same 有权
标题翻译：半导体存储器件和数据错误检测与校正方法相同
公开(公告)号：US08190968B2
公开(公告)日：2012-05-29
申请号：US13099640
申请日：2011-05-03
申请人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
发明人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
IPC分类号： H03M13/00
CPC分类号： G06F11/1008 , G06F11/1076 , G11C8/04 , G11C8/12
摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.
摘要翻译：半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为检测并输出校正的读取数据。

2. 发明授权

US07949928B2 Semiconductor memory device and data error detection and correction method of the same 失效
标题翻译：半导体存储器件和数据错误检测与校正方法相同
公开(公告)号：US07949928B2
公开(公告)日：2011-05-24
申请号：US11773214
申请日：2007-07-03
申请人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
发明人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F11/1076 , G11C8/04 , G11C8/12
摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.
摘要翻译：半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为检测并输出校正的读取数据。

3. 发明申请

US20080109700A1 SEMICONDUCTOR MEMORY DEVICE AND DATA ERROR DETECTION AND CORRECTION METHOD OF THE SAME 失效
标题翻译：半导体存储器件及其数据错误检测及校正方法
公开(公告)号：US20080109700A1
公开(公告)日：2008-05-08
申请号：US11773214
申请日：2007-07-03
申请人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
发明人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1076 , G11C8/04 , G11C8/12
摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.
摘要翻译：半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为检测并输出校正的读取数据。

4. 发明申请

US20110209030A1 SEMICONDUCTOR MEMORY DEVICE AND DATA ERROR DETECTION AND CORRECTION METHOD OF THE SAME 有权
标题翻译：半导体存储器件及其数据错误检测及校正方法
公开(公告)号：US20110209030A1
公开(公告)日：2011-08-25
申请号：US13099640
申请日：2011-05-03
申请人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
发明人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1008 , G06F11/1076 , G11C8/04 , G11C8/12
摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.
摘要翻译：半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为检测并输出校正的读取数据。

5. 发明申请

US20080080240A1 Memory devices and memory systems having the same 有权
标题翻译：具有相同的存储器件和存储器系统
公开(公告)号：US20080080240A1
公开(公告)日：2008-04-03
申请号：US11902424
申请日：2007-09-21
申请人： Kwang-Jin Lee , Won-Seok Lee , Choong-Keun Kwak
发明人： Kwang-Jin Lee , Won-Seok Lee , Choong-Keun Kwak
IPC分类号： G11C16/00
CPC分类号： H01L27/10802 , G11C7/00 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/1084 , G11C11/4063 , H01L21/84 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.
摘要翻译：公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。

6. 发明授权

US07710791B2 Input circuit of a non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件的输入电路
公开(公告)号：US07710791B2
公开(公告)日：2010-05-04
申请号：US11984145
申请日：2007-11-14
申请人： Kwang-jin Lee , Won-Seok Lee , Qi Wang , Hye-Jin Kim , Joon Yong Choi
发明人： Kwang-jin Lee , Won-Seok Lee , Qi Wang , Hye-Jin Kim , Joon Yong Choi
IPC分类号： G11C7/10 , G11C8/06 , G11C7/22 , G11C8/18
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/225 , G11C16/10
摘要： A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.
摘要翻译：非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。

7. 发明授权

US07535760B2 Memory devices and memory systems having the same 有权
标题翻译：具有相同的存储器件和存储器系统
公开(公告)号：US07535760B2
公开(公告)日：2009-05-19
申请号：US11902424
申请日：2007-09-21
申请人： Kwang-Jin Lee , Won-Seok Lee , Choong-Keun Kwak
发明人： Kwang-Jin Lee , Won-Seok Lee , Choong-Keun Kwak
IPC分类号： G11C14/00
CPC分类号： H01L27/10802 , G11C7/00 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/1084 , G11C11/4063 , H01L21/84 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.
摘要翻译：公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。

8. 发明申请

US20080112220A1 Input circuit of a non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件的输入电路
公开(公告)号：US20080112220A1
公开(公告)日：2008-05-15
申请号：US11984145
申请日：2007-11-14
申请人： Kwang-jin Lee , Won-Seok Lee , Qi Wang , Hye-Jin Kim , Joon Yong Choi
发明人： Kwang-jin Lee , Won-Seok Lee , Qi Wang , Hye-Jin Kim , Joon Yong Choi
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/225 , G11C16/10
摘要： A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.
摘要翻译：非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。

9. 发明申请

US20070133267A1 Phase change memory device and method of programming the same 有权
标题翻译：相变存储器件及其编程方法
公开(公告)号：US20070133267A1
公开(公告)日：2007-06-14
申请号：US11319284
申请日：2005-12-29
申请人： Beak-Hyung Cho , Jong-Soo Seo , Won-Seok Lee
发明人： Beak-Hyung Cho , Jong-Soo Seo , Won-Seok Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72 , G11C2213/79
摘要： A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.
摘要翻译：相变存储器件包括具有相变材料的存储单元，向该存储单元提供降压设定电流的写入驱动器，其中降压设定电流包括减小电流幅度的多个连续步骤，以及控制由写入驱动器提供的降压设定电流的持续时间的设定程序控制电路。

10. 发明授权

US09624332B2 Graft monomer composition for thermoplastic transparent resin, composition for thermoplastic transparent resin using the same, and thermoplastic transparent resin having good transparency and color 有权
公开(公告)号：US09624332B2
公开(公告)日：2017-04-18
申请号：US13996462
申请日：2011-12-23
申请人： Jeong-Su Choi , Keun-Hoon Yoo , Hyong-Min Bahn , Won-Seok Lee , Seok-Goo Jang
发明人： Jeong-Su Choi , Keun-Hoon Yoo , Hyong-Min Bahn , Won-Seok Lee , Seok-Goo Jang
IPC分类号： C08F279/02 , C08L51/04 , C08L53/02 , C08L55/02
CPC分类号： C08F279/02 , C08L51/04 , C08L53/02 , C08L55/02 , C08L33/10 , C08F212/10 , C08F220/18 , C08F220/06 , C08F2220/286
摘要： Disclosed is a graft monomer composition for thermoplastic transparent resins, a composition for thermoplastic transparent resins using the same and a thermoplastic transparent resin that exhibits superior transparency and color at low rubber contents. According to the graft monomer composition, the composition for thermoplastic transparent resins and the thermoplastic transparent resin, although the content of rubber in final products increases or the content of rubber in graft copolymers in the preparation of final products increases, the copolymer surrounds the surface of rubber well, thus reducing haze, considerably improving transparency and exhibiting excellent natural color.

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