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1. 发明授权

US11368128B2 Capacitance sensor circuit and semiconductor integrated circuit 有权
公开(公告)号：US11368128B2
公开(公告)日：2022-06-21
申请号：US16795537
申请日：2020-02-19
申请人： LAPIS SEMICONDUCTOR CO., LTD.
发明人： Masayuki Otsuka
IPC分类号： H03F1/30 , H03F3/45 , G01K3/00 , G01K7/34
摘要： A capacitance sensor circuit is provided, including: a capacitance variable capacitor changing from a first capacitance to a second capacitance corresponding to environmental change; a reference capacitor; and an amplifier circuit charging the capacitance variable capacitor via a first node and the reference capacitor via a second node, and outputting a determination signal. In the amplifier circuit, a differential amplification part generates a potential difference signal obtained by amplifying the potential difference between the first and the second nodes; an output part outputs the determination signal based on the potential difference signal; and when the difference between the increase degrees of the potentials of the first and the second nodes is less than a predetermined value, the output part holds and outputs the determination signal immediately before that state and a bias control part stops a current flowing through the differential amplification part.

2. 发明申请

US20200274498A1 CAPACITANCE SENSOR CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20200274498A1
公开(公告)日：2020-08-27
申请号：US16795537
申请日：2020-02-19
申请人： LAPIS SEMICONDUCTOR CO., LTD.
发明人： Masayuki Otsuka
IPC分类号： H03F1/30 , H03F3/45 , G01K7/34 , G01K3/00
摘要： A capacitance sensor circuit is provided, including: a capacitance variable capacitor changing from a first capacitance to a second capacitance corresponding to environmental change; a reference capacitor; and an amplifier circuit charging the capacitance variable capacitor via a first node and the reference capacitor via a second node, and outputting a determination signal. In the amplifier circuit, a differential amplification part generates a potential difference signal obtained by amplifying the potential difference between the first and the second nodes; an output part outputs the determination signal based on the potential difference signal; and when the difference between the increase degrees of the potentials of the first and the second nodes is less than a predetermined value, the output part holds and outputs the determination signal immediately before that state and a bias control part stops a current flowing through the differential amplification part.

3. 发明授权

US10366764B2 Sense amplifier for detecting data read from memory cell 有权
公开(公告)号：US10366764B2
公开(公告)日：2019-07-30
申请号：US15820379
申请日：2017-11-21
申请人： LAPIS Semiconductor Co., Ltd.
发明人： Masayuki Otsuka
IPC分类号： G11C16/04 , G11C16/26 , G11C7/06
摘要： Provided is a sense amplifier circuit for detecting data having been read from a memory cell. The sense amplifier circuit includes: a potential control unit for controlling the potential of a bit line connected to a memory cell; a current amplifier unit for amplifying a readout current flowing from the memory cell to the bit line so as to produce an amplified current; and a detection unit for detecting data having been read from the memory cell on the basis of the amplified current. The potential control unit controls the potential of the bit line in a data readout duration, and the data readout duration includes a current amplification duration, and the current amplifier unit amplifies the readout current in the current amplification duration.

4. 发明授权

US09368227B2 Semiconductor device and test method 有权
标题翻译：半导体器件及测试方法
公开(公告)号：US09368227B2
公开(公告)日：2016-06-14
申请号：US14305601
申请日：2014-06-16
申请人： LAPIS Semiconductor Co., Ltd.
发明人： Masayuki Otsuka
IPC分类号： G01R31/02 , G11C17/18 , G11C29/02 , G01R31/28
CPC分类号： G11C17/18 , G01R31/2853 , G01R31/2856 , G11C29/027
摘要： A test voltage having a first voltage or a second voltage is applied to an output terminal of a complementary fuse that includes a first fuse to one end of which the first voltage is applied and the other end of which serves as the output terminal and a second fuse to one end of which the second voltage is applied and the other end of which is connected to the output terminal. The test voltage then stops being applied. In such a state, whether output data from the output terminal of the complementary fuse coincides with an expected value is determined. The result of determination is output as a test result.
摘要翻译：具有第一电压或第二电压的测试电压被施加到互补熔丝的输出端子，该互补熔丝包括第一熔丝，其一端施加第一电压，其另一端用作输出端子，第二熔断器保险丝的一端施加第二电压，另一端连接到输出端子。然后测试电压停止施加。在这种状态下，确定来自互补熔丝的输出端子的输出数据是否与预期值一致。输出结果作为测试结果。

5. 发明申请

US20220271718A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
公开(公告)号：US20220271718A1
公开(公告)日：2022-08-25
申请号：US17742404
申请日：2022-05-12
申请人： LAPIS Semiconductor Co., Ltd.
发明人： Masayuki Otsuka
IPC分类号： H03F1/30 , H03F3/45 , G01K3/00 , G01K7/34
摘要： A semiconductor integrated circuit is capable of electrically connecting to a capacitance variable capacitor whose electrostatic capacitance changes corresponding to an environmental change between a first and a second capacitances and determines whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed a reference capacitance value. The semiconductor integrated circuit includes a reference capacitor having a fixed electrostatic capacitance between the first capacitance and the second capacitance as the reference capacitance value; and an amplifier circuit, charging the capacitance variable capacitor via a first node and charging the reference capacitor via a second node corresponding to a clock signal, amplifying a potential difference between a potential of the first node and a potential of the second node, and outputting a binary determination signal indicating whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed the reference capacitance value based on the amplified potential difference.

6. 发明授权

US09202589B2 Non-volatile memory and semiconductor device 有权
标题翻译：非易失性存储器和半导体器件
公开(公告)号：US09202589B2
公开(公告)日：2015-12-01
申请号：US13862290
申请日：2013-04-12
申请人： LAPIS SEMICONDUCTOR CO., LTD.
发明人： Masayuki Otsuka
IPC分类号： G11C17/16 , H01L27/112 , G11C17/18 , H01L29/866
CPC分类号： H01L27/11206 , G11C17/16 , G11C17/18 , H01L29/866
摘要： There is provided a non-volatile memory including: plural zener zap devices, each including a cathode region and an anode region formed in a well; and a metal wiring line that is formed above the plural zener zap devices, that is commonly connected to each of the cathode regions, and that supplies a write voltage to each of the zener zap devices.
摘要翻译：提供了一种非易失性存储器，包括：多个齐纳zap器件，每个齐纳器器件包括形成在阱中的阴极区域和阳极区域; 以及形成在多个齐纳钳位装置上方的金属布线，其通常连接到每个阴极区域，并且向每个齐纳扎带器件提供写入电压。

7. 发明授权

US10673326B2 Semiconductor device including boosting circuit with plural pump circuits 审中-公开
公开(公告)号：US10673326B2
公开(公告)日：2020-06-02
申请号：US16202006
申请日：2018-11-27
申请人： LAPIS SEMICONDUCTOR CO., LTD.
发明人： Masayuki Otsuka
IPC分类号： H01L23/522 , H02M3/07 , G11C16/30 , H01L27/06 , G11C5/14
摘要： A semiconductor device including: a semiconductor substrate; at least one circuit block provided on a main surface of the semiconductor substrate and having a predetermined function; a wiring layer including plural metal layers that connect the circuit block; and plural capacitors including a first capacitor connected to the circuit block and that uses the plurality of metal layers, and a second capacitor that uses an active area disposed within the main surface of the semiconductor substrate, wherein at least one of the first capacitor and at least one of the second capacitor are stacked in a stacking direction of layers of the semiconductor.

8. 发明授权

US09928921B2 Non-volatile memory, semiconductor device and reading method 有权
公开(公告)号：US09928921B2
公开(公告)日：2018-03-27
申请号：US15042730
申请日：2016-02-12
申请人： LAPIS Semiconductor Co., Ltd.
发明人： Masayuki Otsuka
IPC分类号： G11C17/16 , G11C17/18
CPC分类号： G11C17/18 , G11C17/16
摘要： There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector.

9. 发明授权

US09602003B2 Voltage regulator, semiconductor device, and voltage generation method for voltage regulator 有权
公开(公告)号：US09602003B2
公开(公告)日：2017-03-21
申请号：US15133215
申请日：2016-04-19
申请人： LAPIS Semiconductor Co., Ltd.
发明人： Masayuki Otsuka
IPC分类号： H02M3/158
CPC分类号： H02M3/158 , G11C5/147 , G11C5/148
摘要： A voltage regulator includes: a drive voltage generating part for generating a drive voltage and then apply the drive voltage to a drive line; an output transistor for outputting a voltage corresponding to a voltage value of the drive line as the internal source voltage; and a compulsory drive circuit including a capacitor element configured to receive the source voltage at one end, a first switching element for receiving a ground voltage and applying the ground voltage to the other end of the capacitor element by being set in an ON state over a period in which the selected operational mode is the standby mode, and a second switching element that connects the other end of the capacitor element to the drive line only for a predetermined period in an ON state when the operational mode transitions from the standby mode to the active mode.

10. 发明授权

US09461056B2 Non-volatile memory and semiconductor device 有权
公开(公告)号：US09461056B2
公开(公告)日：2016-10-04
申请号：US14930827
申请日：2015-11-03
申请人： LAPIS SEMICONDUCTOR CO., LTD.
发明人： Masayuki Otsuka
IPC分类号： G11C17/16 , H01L27/112 , G11C17/18 , H01L29/866
CPC分类号： H01L27/11206 , G11C17/16 , G11C17/18 , H01L29/866
摘要： There is provided a non-volatile memory including: plural zener zap devices, each including a cathode region and an anode region formed in a well; and a metal wiring line that is formed above the plural zener zap devices, that is commonly connected to each of the cathode regions, and that supplies a write voltage to each of the zener zap devices.

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