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1. 发明申请

US20150263732A1 SYSTEMS AND METHODS FOR VOLTAGE LEVEL SHIFTING IN A DEVICE 有权
标题翻译：用于设备中电压水平移位的系统和方法
公开(公告)号：US20150263732A1
公开(公告)日：2015-09-17
申请号：US14211084
申请日：2014-03-14
申请人： LSI Corporation
发明人： Dharmendra Kumar Rai , Disha Singh
IPC分类号： H03K19/0175 , H03K19/0944 , H03K19/00 , H03K19/0948
CPC分类号： H03K19/017509 , H03K19/0013 , H03K19/018521 , H03K19/0944 , H03K19/0948
摘要： Level shifters are disclosed for high performance sub-micron IC designs. One embodiment is a level shifting device that comprises a first input circuit that toggles a first internal signal between a logical zero of a first voltage range and a logical one of a second voltage range based on an input data signal and an output data signal, and a second input circuit that toggles a second internal signal between a logical zero of the second voltage range and a logical one of the first voltage range based on the input data signal and the output data signal. An output circuit of the device toggles the output data signal between a logical zero of the second voltage range and a logical one of the second voltage range based on the first internal signal, the second internal signal, and a compliment of the input data signal.
摘要翻译：公开了用于高性能亚微米IC设计的电平移位器。一个实施例是电平移位装置，其包括第一输入电路，其基于输入数据信号和输出数据信号，在第一电压范围的逻辑零点和第二电压范围的逻辑零之间切换第一内部信号，以及第二输入电路，其基于输入数据信号和输出数据信号，在第二电压范围的逻辑零点与第一电压范围的逻辑0之间切换第二内部信号。设备的输出电路基于第一内部信号，第二内部信号和输入数据信号的补充，将输出数据信号切换到第二电压范围的逻辑零点与第二电压范围的逻辑零点之间。

2. 发明授权

US08792293B2 Single-ended sense amplifier for solid-state memories 有权
标题翻译：用于固态存储器的单端读出放大器
公开(公告)号：US08792293B2
公开(公告)日：2014-07-29
申请号：US13661250
申请日：2012-10-26
申请人： LSI Corporation
发明人： Sahilpreet Singh , Disha Singh
IPC分类号： G11C7/00 , G11C11/4091 , G11C7/06
CPC分类号： G11C11/4091 , G11C7/02 , G11C7/06 , G11C7/062 , G11C7/067 , G11C7/12
摘要： Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an input coupled to the internal node and an output coupled to an output of the sense amplifier and the second capacitor is coupled between the internal node and a control node. When data is to be read from the memory, the second capacitor forces a small voltage reduction onto the intermediate node, helping the sense amplifier resolve the data value stored in the memory cell.
摘要翻译：所描述的实施例提供具有至少一个读出放大器的存储器。读出放大器具有第一电容器，反相放大器，开关，放大器和第二电容器。第一电容器耦合在感测放大器的输入端和第一节点之间。反相放大器具有耦合到第一节点的输入和耦合到内部节点的输出，并且开关耦合在反相放大器的输入和输出之间。放大器具有耦合到内部节点的输入和耦合到读出放大器的输出的输出，第二电容耦合在内部节点和控制节点之间。当要从存储器读取数据时，第二电容器迫使中间节点上的电压降低，帮助读出放大器解析存储在存储单元中的数据值。

3. 发明授权

US09584123B2 Systems and methods for voltage level shifting in a device 有权
标题翻译：设备中电压电平转换的系统和方法
公开(公告)号：US09584123B2
公开(公告)日：2017-02-28
申请号：US14211084
申请日：2014-03-14
申请人： LSI Corporation
发明人： Dharmendra Kumar Rai , Disha Singh
IPC分类号： H03K19/0175 , H03K19/0948 , H03K19/0944 , H03K19/00
CPC分类号： H03K19/017509 , H03K19/0013 , H03K19/018521 , H03K19/0944 , H03K19/0948
摘要： Level shifters are disclosed for high performance sub-micron IC designs. One embodiment is a level shifting device that comprises a first input circuit that toggles a first internal signal between a logical zero of a first voltage range and a logical one of a second voltage range based on an input data signal and an output data signal, and a second input circuit that toggles a second internal signal between a logical zero of the second voltage range and a logical one of the first voltage range based on the input data signal and the output data signal. An output circuit of the device toggles the output data signal between a logical zero of the second voltage range and a logical one of the second voltage range based on the first internal signal, the second internal signal, and a compliment of the input data signal.
摘要翻译：公开了用于高性能亚微米IC设计的电平移位器。一个实施例是电平移位装置，其包括第一输入电路，其基于输入数据信号和输出数据信号，在第一电压范围的逻辑零点和第二电压范围的逻辑零之间切换第一内部信号，以及第二输入电路，其基于输入数据信号和输出数据信号，在第二电压范围的逻辑零点与第一电压范围的逻辑0之间切换第二内部信号。设备的输出电路基于第一内部信号，第二内部信号和输入数据信号的补充，将输出数据信号切换到第二电压范围的逻辑零点与第二电压范围的逻辑零点之间。

4. 发明申请

US20140119093A1 Single-Ended Sense Amplifier for Solid-State Memories 有权
标题翻译：用于固态存储器的单端感测放大器
公开(公告)号：US20140119093A1
公开(公告)日：2014-05-01
申请号：US13661250
申请日：2012-10-26
申请人： LSI CORPORATION
发明人： Sahilpreet Singh , Disha Singh
IPC分类号： G11C7/06 , G11C17/12 , G11C7/12
CPC分类号： G11C11/4091 , G11C7/02 , G11C7/06 , G11C7/062 , G11C7/067 , G11C7/12
摘要： Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an input coupled to the internal node and an output coupled to an output of the sense amplifier and the second capacitor is coupled between the internal node and a control node. When data is to be read from the memory, the second capacitor forces a small voltage reduction onto the intermediate node, helping the sense amplifier resolve the data value stored in the memory cell.
摘要翻译：所描述的实施例提供具有至少一个读出放大器的存储器。读出放大器具有第一电容器，反相放大器，开关，放大器和第二电容器。第一电容器耦合在感测放大器的输入端和第一节点之间。反相放大器具有耦合到第一节点的输入和耦合到内部节点的输出，并且开关耦合在反相放大器的输入和输出之间。放大器具有耦合到内部节点的输入和耦合到读出放大器的输出的输出，第二电容耦合在内部节点和控制节点之间。当要从存储器读取数据时，第二电容器迫使中间节点上的电压降低，帮助读出放大器解析存储在存储单元中的数据值。

5. 发明申请

US20140241061A1 FAST ACCESS WITH LOW LEAKAGE AND LOW POWER TECHNIQUE FOR READ ONLY MEMORY DEVICES 有权
标题翻译：具有低泄漏和低功率技术的快速访问，用于只读存储器件
公开(公告)号：US20140241061A1
公开(公告)日：2014-08-28
申请号：US13775942
申请日：2013-02-25
申请人： LSI CORPORATION
发明人： Rajiv Kumar Roy , Disha Singh , Sahilpreet Singh
IPC分类号： G11C16/30
CPC分类号： G11C17/12
摘要： A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.
摘要翻译：一种只读存储器（ROM）和方法，用于提供较高的运行速度，减少泄漏，无核心单元备用泄漏和低功耗。 ROM单元（NMOS）的源极连接到虚拟接地线（VNGD）而不是VSS。因此，ROM单元可以可操作地耦合到位线，字线和虚拟地，其也用作列选择信号。 ROM的布置使得所选列的虚拟地被下拉到接地电压。未选择的列虚拟接地可以保持在电源电压，以确保不需要的列不会有任何子阈值电流（如Vds = 0）。由于在访问时间路径中不进行位线预充电，所以ROM实现了高的运行速度，同时减少了泄漏和低功耗。

6. 发明授权

US09064583B2 Fast access with low leakage and low power technique for read only memory devices 有权
标题翻译：以低泄漏和低功耗技术快速访问只读存储器件
公开(公告)号：US09064583B2
公开(公告)日：2015-06-23
申请号：US13775942
申请日：2013-02-25
申请人： LSI Corporation
发明人： Rajiv Kumar Roy , Disha Singh , Sahilpreet Singh
IPC分类号： G11C11/34 , G11C17/12
CPC分类号： G11C17/12
摘要： A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.
摘要翻译：一种只读存储器（ROM）和方法，用于提供较高的运行速度，减少泄漏，无核心单元备用泄漏和低功耗。 ROM单元（NMOS）的源极连接到虚拟接地线（VNGD）而不是VSS。因此，ROM单元可以可操作地耦合到位线，字线和虚拟地，其也用作列选择信号。 ROM的布置使得所选列的虚拟地被下拉到接地电压。未选择的列虚拟接地可以保持在电源电压，以确保不需要的列不会有任何子阈值电流（如Vds = 0）。由于在访问时间路径中不进行位线预充电，所以ROM实现了高的运行速度，同时减少了泄漏和低功耗。

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