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1. 发明授权

US07840316B2 Limited authority and full authority mode fly-by-wire flight control surface actuation control system 有权
标题翻译：有限权限和全权限模式飞控飞行控制面启动控制系统
公开(公告)号：US07840316B2
公开(公告)日：2010-11-23
申请号：US11957665
申请日：2007-12-17
申请人： Larry J. Yount , Gerald B. Kelley , Kent A. Stange , Welsh C. Pond
发明人： Larry J. Yount , Gerald B. Kelley , Kent A. Stange , Welsh C. Pond
IPC分类号： G01C23/00
CPC分类号： B64C13/503 , G05D1/0061
摘要： An aircraft flight control surface actuation control system includes an actuator control unit and a flight control module. The actuator control unit includes at least two independent actuator control channels to generate limited authority flight control surface actuator commands based on pilot inceptor position signals and flight control augmentation data. The flight control module supplies the flight control augmentation data to each of the independent actuator control channels, determines operability of each of the actuator control channels and, based on the determined operability of each independent actuator control channel, selectively prevents one of the independent actuator control channels from supplying the limited authority flight control surface actuator commands. The flight control module may also generate full authority flight control surface actuator commands for supply to flight control surface actuators.
摘要翻译：飞行器飞行控制表面致动控制系统包括致动器控制单元和飞行控制模块。致动器控制单元包括至少两个独立的致动器控制通道，用于基于导向受体位置信号和飞行控制增强数据产生有限的授权的飞行控制表面致动器命令。飞行控制模块将飞行控制增强数据提供给每个独立的致动器控制通道，确定每个致动器控制通道的可操作性，并且基于所确定的每个独立致动器控制通道的可操作性，选择性地防止独立致动器控制提供有限授权飞行控制表面执行器命令的通道。飞行控制模块还可以产生用于向飞行控制表面致动器供应的完全授权的飞行控制表面致动器命令。

2. 发明申请

US20090152404A1 LIMITED AUTHORITY AND FULL AUTHORITY MODE FLY-BY-WIRE FLIGHT CONTROL SURFACE ACTUATION CONTROL SYSTEM 有权
标题翻译：有限责任权和全权证模式飞行式飞行控制表面执行控制系统
公开(公告)号：US20090152404A1
公开(公告)日：2009-06-18
申请号：US11957665
申请日：2007-12-17
申请人： Larry J. Yount , Gerald B. Kelley , Kent A. Stange , Welsh C. Pond
发明人： Larry J. Yount , Gerald B. Kelley , Kent A. Stange , Welsh C. Pond
IPC分类号： G05D1/00
CPC分类号： B64C13/503 , G05D1/0061
摘要： An aircraft flight control surface actuation control system includes an actuator control unit and a flight control module. The actuator control unit includes at least two independent actuator control channels to generate limited authority flight control surface actuator commands based on pilot inceptor position signals and flight control augmentation data. The flight control module supplies the flight control augmentation data to each of the independent actuator control channels, determines operability of each of the actuator control channels and, based on the determined operability of each independent actuator control channel, selectively prevents one of the independent actuator control channels from supplying the limited authority flight control surface actuator commands. The flight control module may also generate full authority flight control surface actuator commands for supply to flight control surface actuators.
摘要翻译：飞行器飞行控制表面致动控制系统包括致动器控制单元和飞行控制模块。致动器控制单元包括至少两个独立的致动器控制通道，用于基于导向受体位置信号和飞行控制增强数据产生有限的授权的飞行控制表面致动器命令。飞行控制模块将飞行控制增强数据提供给每个独立的致动器控制通道，确定每个致动器控制通道的可操作性，并且基于所确定的每个独立致动器控制通道的可操作性，选择性地防止独立致动器控制提供有限授权飞行控制表面执行器命令的通道。飞行控制模块还可以产生用于向飞行控制表面致动器供应的完全授权的飞行控制表面致动器命令。

3. 发明申请

US20100064092A1 INTERFACE FOR WRITING TO MEMORIES HAVING DIFFERENT WRITE TIMES 失效
标题翻译：用于写入具有不同写入时间的记忆的界面
公开(公告)号：US20100064092A1
公开(公告)日：2010-03-11
申请号：US11132860
申请日：2005-05-19
申请人： Richard F. Hess , Kent A. Stange
发明人： Richard F. Hess , Kent A. Stange
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C29/02 , G06F11/141 , G06F13/1694 , G11C29/022 , G11C29/028 , G11C29/50012
摘要： An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device.
摘要翻译：描述具有不同写入时间的存储器之间的接口。接口包括用于在由第一存储器设备的处理器进行的存储器访问期间捕获地址和数据信息的锁存器。接口还包括用于提供帧管理的索引计数器。接口还包括用于确定要写入第二存储器设备中的数据和地址生成逻辑的可变标识阵列逻辑，以确定数据将被存储在第二存储器设备中的位置。此外，该接口包括数据有效性逻辑，以确保写入第二存储器件的数据有效。结果，处理器可以基本上实时地操作，并且可以使用存储在第二存储器设备中的数据检测事件不正常之后恢复自身。

4. 发明授权

US07698511B2 Interface for writing to memories having different write times 失效
标题翻译：用于写入具有不同写入时间的存储器的接口
公开(公告)号：US07698511B2
公开(公告)日：2010-04-13
申请号：US11132860
申请日：2005-05-19
申请人： Richard F. Hess , Kent A. Stange
发明人： Richard F. Hess , Kent A. Stange
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F11/00 , G11C7/10
CPC分类号： G11C29/02 , G06F11/141 , G06F13/1694 , G11C29/022 , G11C29/028 , G11C29/50012
摘要： An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device.
摘要翻译：描述具有不同写入时间的存储器之间的接口。接口包括用于在由第一存储器设备的处理器进行的存储器访问期间捕获地址和数据信息的锁存器。接口还包括用于提供帧管理的索引计数器。接口还包括用于确定要写入第二存储器设备中的数据和地址生成逻辑的可变标识阵列逻辑，以确定数据将被存储在第二存储器设备中的位置。此外，该接口包括数据有效性逻辑，以确保写入第二存储器件的数据有效。结果，处理器可以基本上实时地操作，并且可以使用存储在第二存储器设备中的数据检测事件不正常之后恢复自身。

5. 发明授权

US07971095B2 Fault recovery for real-time, multi-tasking computer system 有权
标题翻译：实时，多任务计算机系统的故障恢复
公开(公告)号：US07971095B2
公开(公告)日：2011-06-28
申请号：US11058764
申请日：2005-02-16
申请人： Richard Hess , Gerald B. Kelly , Randy Rogers , Kent A. Stange
发明人： Richard Hess , Gerald B. Kelly , Randy Rogers , Kent A. Stange
IPC分类号： G06F11/00
CPC分类号： G06F11/1438 , G06F11/1645 , G06F11/1658 , G06F11/1679
摘要： System and methods for providing a recoverable real time multi-tasking computer system are disclosed. In one embodiment, a system comprises a real time computing environment, wherein the real time computing environment is adapted to execute one or more applications and wherein each application is time and space partitioned. The system further comprises a fault detection system adapted to detect one or more faults affecting the real time computing environment and a fault recovery system, wherein upon the detection of a fault the fault recovery system is adapted to restore a backup set of state variables.
摘要翻译：公开了用于提供可恢复的实时多任务计算机系统的系统和方法。在一个实施例中，系统包括实时计算环境，其中实时计算环境适于执行一个或多个应用，并且其中每个应用程序是时间和空间分区的。该系统还包括适于检测影响实时计算环境的一个或多个故障的故障检测系统和故障恢复系统，其中，在检测到故障时，故障恢复系统适于恢复状态变量的备份集。

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