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1. 发明申请

US20110197171A1 COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL 失效
标题翻译：计算机辅助设计系统，用于自动扫描合成记录级别
公开(公告)号：US20110197171A1
公开(公告)日：2011-08-11
申请号：US13030410
申请日：2011-02-18
申请人： Laung-Terng (L.-T.) WANG , Xiaoqing Wen
发明人： Laung-Terng (L.-T.) WANG , Xiaoqing Wen
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31704 , G01R31/318314 , G01R31/318364 , G01R31/318583 , G01R31/318594 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F2217/14
摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
摘要翻译：一种在寄存器传输级（RTL）下自动扫描合成的方法和系统。该方法和系统将产生在RTL建模的扫描HDL代码，用于在RTL建模的集成电路。该方法和系统包括执行RTL可测试性分析，时钟域最小化，扫描选择，测试点选择，扫描修复和测试点插入，扫描替换和扫描拼接，扫描提取，交互式扫描调试，交互式扫描修复的计算机实现步骤和冲洗/随机测试台生成。此外，本发明还包括通过逐个模块执行扫描合成然后将这些扫描的模块拼接在一起的层次扫描合成的方法和系统。本发明还包括将扫描HDL码与其他测试（DFT）HDL码进行集成和验证，包括边界扫描和逻辑BIST（内置自检）。

2. 发明授权

US07735049B2 Mask network design for scan-based integrated circuits 失效
标题翻译：基于扫描的集成电路的掩模网络设计
公开(公告)号：US07735049B2
公开(公告)日：2010-06-08
申请号：US11350949
申请日：2006-02-10
申请人： Laung-Terng (L.-T.) Wang , Xiaoqing Wen , Boryau (Jack) Sheu
发明人： Laung-Terng (L.-T.) Wang , Xiaoqing Wen , Boryau (Jack) Sheu
IPC分类号： G06F17/50 , G01R31/3177 , G01R31/3181 , G01R31/3185
CPC分类号： G01R31/318547 , G01R31/318536
摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.
摘要翻译：一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获的扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入。还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。

3. 发明申请

US20080276141A1 Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit 审中-公开
标题翻译：用于在基于扫描的集成电路中广播扫描图案的方法和装置
公开(公告)号：US20080276141A1
公开(公告)日：2008-11-06
申请号：US12216639
申请日：2008-07-09
申请人： Laung-Terng(L.-T.) Wang , Xiaoqing Wen , Shyh-Horng Lin , Khader S. Abdel-Hafez
发明人： Laung-Terng(L.-T.) Wang , Xiaoqing Wen , Shyh-Horng Lin , Khader S. Abdel-Hafez
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/318533 , G01R31/31926
摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor.
摘要翻译：用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。虚拟扫描控制器控制广播机构的操作。系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。进一步提出方法来重新排列所选扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且合成广播器和压缩器。

4. 发明授权

US07007213B2 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test 失效
公开(公告)号：US07007213B2
公开(公告)日：2006-02-28
申请号：US10067372
申请日：2002-02-07
申请人： Laung-Terng (L.-T.) Wang , Po-Ching Hsu , Shih-Chia Kao , Meng-Chyi Lin , Hsin-Po Wang , Hao-Jan Chao , Xiaoqing Wen
发明人： Laung-Terng (L.-T.) Wang , Po-Ching Hsu , Shih-Chia Kao , Meng-Chyi Lin , Hsin-Po Wang , Hao-Jan Chao , Xiaoqing Wen
IPC分类号： G01R31/28
CPC分类号： G06F17/5022 , G01R31/31704 , G01R31/318552 , G01R31/318594 , G06F17/5031 , G06F17/505
摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

5. 发明申请

US20120246604A1 COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL 失效
标题翻译：计算机辅助设计系统，用于自动扫描合成记录级别
公开(公告)号：US20120246604A1
公开(公告)日：2012-09-27
申请号：US13490721
申请日：2012-06-07
申请人： Laung-Terng (L. -T.) WANG , Augusli Kifli , Fei-Sheng Hsu , Shih-Chia Kao , Xiaoqing Wen , Shyh-Horag Lin , Hsin-Po Wang
发明人： Laung-Terng (L. -T.) WANG , Augusli Kifli , Fei-Sheng Hsu , Shih-Chia Kao , Xiaoqing Wen , Shyh-Horag Lin , Hsin-Po Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31704 , G01R31/318314 , G01R31/318364 , G01R31/318583 , G01R31/318594 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F2217/14
摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
摘要翻译：一种在寄存器传输级（RTL）下自动扫描合成的方法和系统。该方法和系统将产生在RTL建模的扫描HDL代码，用于在RTL建模的集成电路。该方法和系统包括执行RTL可测试性分析，时钟域最小化，扫描选择，测试点选择，扫描修复和测试点插入，扫描替换和扫描拼接，扫描提取，交互式扫描调试，交互式扫描修复的计算机实现步骤和冲洗/随机测试台生成。此外，本发明还包括通过逐个模块执行扫描合成然后将这些扫描的模块拼接在一起的层次扫描合成的方法和系统。本发明还包括将扫描HDL码与其他测试（DFT）HDL码进行集成和验证，包括边界扫描和逻辑BIST（内置自检）。

6. 发明授权

US07444567B2 Method and apparatus for unifying self-test with scan-test during prototype debug and production test 失效
标题翻译：在原型调试和生产测试过程中用扫描测试统一自检的方法和装置
公开(公告)号：US07444567B2
公开(公告)日：2008-10-28
申请号：US10406592
申请日：2003-04-04
申请人： Laung-Terng (L.-T.) Wang , Xiaoqing Wen , Khader S. Abdel-Hafez , Shyh-Horng Lin , Hsin-Po Wang , Ming-Tung Chang , Po-Ching Hsu , Shih-Chia Kao , Meng-Chyi Lin , Chi-Chan Hsu
发明人： Laung-Terng (L.-T.) Wang , Xiaoqing Wen , Khader S. Abdel-Hafez , Shyh-Horng Lin , Hsin-Po Wang , Ming-Tung Chang , Po-Ching Hsu , Shih-Chia Kao , Meng-Chyi Lin , Chi-Chan Hsu
IPC分类号： G01R31/28
CPC分类号： G06F11/27 , G01R31/318586 , G01R31/318594
摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.
摘要翻译：一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

7. 发明授权

US07331032B2 Computer-aided design system to automate scan synthesis at register-transfer level 失效
公开(公告)号：US07331032B2
公开(公告)日：2008-02-12
申请号：US11111908
申请日：2005-04-22
申请人： Laung-Terng (L. -T.) Wang , Augusli Kifli , Fei-Sheng Hsu , Xiaoqing Wen , Shih-Chia Kao , Shyh-Horng Lin , Hsin-Po Wang
发明人： Laung-Terng (L. -T.) Wang , Augusli Kifli , Fei-Sheng Hsu , Xiaoqing Wen , Shih-Chia Kao , Shyh-Horng Lin , Hsin-Po Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31704 , G01R31/318314 , G01R31/318364 , G01R31/318583 , G01R31/318594 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F2217/14
摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

8. 发明授权

US07779322B1 Compacting test responses using X-driven compactor 有权
标题翻译：使用X驱动压实机压实测试响应
公开(公告)号：US07779322B1
公开(公告)日：2010-08-17
申请号：US11898070
申请日：2007-09-07
申请人： Zhigang Wang , Laung-Terng (L.-T.) Wang , Shianling Wu , Xiaoqing Wen , Boryau (Jack) Sheu , Zhigang Jiang
发明人： Zhigang Wang , Laung-Terng (L.-T.) Wang , Shianling Wu , Xiaoqing Wen , Boryau (Jack) Sheu , Zhigang Jiang
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A method and apparatus for compacting test responses containing unknown values in a scan-based integrated circuit. The proposed X-driven compactor comprises a chain-switching matrix block and a space compaction logic block. The chain-switching matrix block switches the internal scan chain outputs before feeding them to the space compaction logic block for compaction so as to minimize X-induced masking and error masking. The X-driven compactor further selectively includes a finite-memory compaction logic block to further compact the outputs of the space compaction logic block.
摘要翻译：一种在基于扫描的集成电路中压缩包含未知值的测试响应的方法和装置。所提出的X驱动压实机包括链切换矩阵块和空间压缩逻辑块。链路切换矩阵块在将它们馈送到空间压缩逻辑块以进行压缩之前切换内部扫描链输出，以最小化X诱导的掩蔽和错误掩蔽。 X驱动压实机还选择性地包括有限存储器压缩逻辑块，以进一步压缩空间压缩逻辑块的输出。

9. 发明授权

US06954887B2 Multiple-capture DFT system for scan-based integrated circuits 失效
公开(公告)号：US06954887B2
公开(公告)日：2005-10-11
申请号：US10101517
申请日：2002-03-20
申请人： Laung-Terng (L.-T.) Wang , Meng-Chyi Lin , Xiaoqing Wen , Hsin-Po Wang , Chi-Chan Hsu , Shih-Chia Kao , Fei-Sheng Hsu
发明人： Laung-Terng (L.-T.) Wang , Meng-Chyi Lin , Xiaoqing Wen , Hsin-Po Wang , Chi-Chan Hsu , Shih-Chia Kao , Fei-Sheng Hsu
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318594 , G01R31/31704 , G01R31/318552 , G01R31/31858
摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

10. 发明授权

US08543950B2 Computer-aided design system to automate scan synthesis at register-transfer level 失效
公开(公告)号：US08543950B2
公开(公告)日：2013-09-24
申请号：US13490721
申请日：2012-06-07
申请人： Laung-Terng (L.-T.) Wang , Augusli Kifli , Fei-Sheng Hsu , Shih-Chia Kao , Xiaoqing Wen , Shyh-Horng Lin , Hsin-Po Wang
发明人： Laung-Terng (L.-T.) Wang , Augusli Kifli , Fei-Sheng Hsu , Shih-Chia Kao , Xiaoqing Wen , Shyh-Horng Lin , Hsin-Po Wang
IPC分类号： G06F17/50 , G06F11/00 , G01R31/28
CPC分类号： G06F17/505 , G01R31/31704 , G01R31/318314 , G01R31/318364 , G01R31/318583 , G01R31/318594 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F2217/14
摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

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