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1. 发明申请

US20180120377A1 LOGIC ANALYZER AND PROBE THEREOF 审中-公开
公开(公告)号：US20180120377A1
公开(公告)日：2018-05-03
申请号：US15326440
申请日：2015-05-18
申请人： ZEROPLUS TECHNOLOGY CO., LTD.
发明人： CHIU-HAO CHENG
IPC分类号： G01R31/3177 , G01R31/319 , G01R31/3183 , G01R31/28
CPC分类号： G01R31/3177 , G01R1/06788 , G01R13/02 , G01R31/2808 , G01R31/318314 , G01R31/31905
摘要： A logic analyzer includes a probe, a first transmission line, a display, a second transmission line, and a processing unit. The probe is adapted to abut against a DUT to retrieve digital signals therefrom. The first transmission line is electrically connected to the probe. The display is provided on the probe. The second transmission line is electrically connected to the display. The processing unit is electrically connected to the first transmission line and the second transmission line, and is adapted to be electrically connected to a computer. The digital signal retrieved by the probe would be transmitted to the processing unit through the first transmission line to be analyzed therein. After completing the analysis, an analysis result would be transmitted to the computer for display. Meanwhile, a part of the analysis result is transmitted to the display through the second transmission line to be displayed thereon.

2. 发明授权

US09933486B2 Apparatus and method of generating test pattern, test system using the same, and computer program therefor 有权
公开(公告)号：US09933486B2
公开(公告)日：2018-04-03
申请号：US14862386
申请日：2015-09-23
申请人： SK hynix Inc.
发明人： Jae Seok Kang
IPC分类号： G06F17/50 , G01R31/319 , G01R31/317 , G01R31/3183
CPC分类号： G01R31/31919 , G01R31/31704 , G01R31/318314
摘要： A test pattern generation apparatus includes an input unit, an output unit, and a pattern generating unit configured to, when a source code based on a system description language is created through the input unit, store an execution file created from the source code, generate a test pattern from the execution file according to an external command for testing a semiconductor apparatus as a DUT, and output the generated test pattern through the output unit.

3. 发明申请

US20170193154A1 Low Cost Design for Test Architecture 审中-公开
公开(公告)号：US20170193154A1
公开(公告)日：2017-07-06
申请号：US15397567
申请日：2017-01-03
申请人： Chinsong Sul
发明人： Chinsong Sul
IPC分类号： G06F17/50
CPC分类号： G01R31/318364 , G01R31/31704 , G01R31/318314
摘要： A Design-for-testability method based on composition of test patterns copes with increasing test complexity and cost metric of a large system. System-level structural test patterns from test patterns of constituent subsystems, cores and design IPs are constructed without requiring their design netlists. The delivered test patterns can be utilized 100% in the testing of system. The system-level test pattern is delivered to the device under test, the subsystem test patterns can be scheduled and applied continuously without being interleaved by test deliveries until all of the subsystem test patterns are exercised. Absence of design netlist requirement allows uniform integration of external and internal IPs regardless of availability of test isolation logic or design details. Concurrent test of constituents and their mutual independence in scan operations allows implicit distribution of test protocol signals such as scan enable (SE) and the scan clocks. The method enables at-speed testing of memory shadow logic.

4. 发明申请

US20160139202A1 TESTBENCH BUILDER, SYSTEM, DEVICE AND METHOD INCLUDING LATENCY DETECTION 有权
标题翻译：测试建筑物，系统，设备和方法，包括延迟检测
公开(公告)号：US20160139202A1
公开(公告)日：2016-05-19
申请号：US14672025
申请日：2015-03-27
申请人： XPLIANT, INC.
发明人： Saurin Patel , Nimalan Siva , Keqin Kenneth Han
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31727 , G01R31/318314 , G06F11/2273 , G06F11/261 , G06F11/263 , G06F11/364 , G06F17/5009 , G06F17/5081 , H04L43/14 , H04L43/50
摘要： A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.
摘要翻译：用于测试被测设备（DUT）的测试台，其中测试台具有验证环境，其包括DUT需要从其接收输入和/或传输输出的每个接口的参考模型，记分板和定制代理。测试平台系统能够由测试平台构建器生成，该测试平台构建器自动创建记分板，参考模型，调度程序和通用代理，包括通用驱动程序，回送端口，顺控程序和/或每个界面的通用监视器，然后自动定制通用代理基于其对应的接口，使代理符合DUT的接口要求。

5. 发明授权

US09280291B2 Method for data accessing and memory writing for logic analyzer 有权
标题翻译：逻辑分析仪的数据访问和存储器写入方法
公开(公告)号：US09280291B2
公开(公告)日：2016-03-08
申请号：US13761561
申请日：2013-02-07
申请人： ZEROPLUS TECHNOLOGY CO., LTD.
发明人： Chiu-Hao Cheng
IPC分类号： G06F12/00 , G06F3/06 , G01R31/3177 , G11C29/56 , G01R31/3183
CPC分类号： G06F3/0611 , G01R31/3177 , G01R31/318314 , G11C29/56 , G11C2029/5602
摘要： A method of fetching digital data and writing the digital data into a memory of a logic analyzer, which comprises the steps: designate at least a first region and a second region in a memory; set a first triggering condition and a second triggering condition; fetch digital data continuously and write it into the memory while analyzing; and then write first test data which have an identification to satisfy the first triggering condition into the first region, and write second test data which have an identification to satisfy the second triggering condition into the second region. And once the first test data or the second test data are found, stop writing the digital data into the corresponding regions.
摘要翻译：一种获取数字数据并将数字数据写入逻辑分析仪的存储器的方法，包括以下步骤：指定存储器中的至少第一区域和第二区域; 设置第一触发条件和第二触发条件; 连续读取数字数据，并在分析时将其写入存储器; 然后将具有满足第一触发条件的识别的第一测试数据写入第一区域，并将具有满足第二触发条件的识别的第二测试数据写入第二区域。一旦找到第一个测试数据或第二个测试数据，就停止将数字数据写入相应的区域。

6. 发明申请

US20140317450A1 PRETEST SETUP PLANNING 有权
标题翻译：先进的设置规划
公开(公告)号：US20140317450A1
公开(公告)日：2014-10-23
申请号：US14243908
申请日：2014-04-03
申请人： International Business Machines Corporation
发明人： Howard M. Hess , Rachel Tzoref-Brill , Aviad Zlotnick
IPC分类号： G06F11/36
CPC分类号： G06F11/3684 , G01R31/318314
摘要： A computer-implemented method comprising: obtaining a description of a test suite which comprises a plurality of tests, wherein each test of the test suite is described by values of functional attributes, wherein at least a portion of the functional attributes are setup-related attributes, wherein a combination of values of the setup-relates attributes potentially indicate a setup activity to be performed prior to executing the test to set up a test environment for the test. Identifying, based on the description of the test suite, a setup activity that is associated with two or more tests, wherein the setup activity is configured to set up a component of the test environment, wherein the identifying is performed by a processor. Providing a first instruction to perform the setup activity prior to executing a first test of the two or more tests. And, providing a second instruction to reuse the component of the test environment when executing additional tests of the two or more tests, whereby avoiding performing duplicate setup activities.
摘要翻译：一种计算机实现的方法，包括：获得包括多个测试的测试套件的描述，其中测试套件的每个测试由功能属性的值描述，其中功能属性的至少一部分是与设置有关的属性其中，所述设置相关属性的值的组合潜在地指示在执行测试之前要执行的建立活动以建立用于测试的测试环境。基于测试套件的描述识别与两个或更多个测试相关联的设置活动，其中所述设置活动被配置为设置所述测试环境的组件，其中所述识别由处理器执行。提供在执行两个或更多个测试的第一测试之前执行设置活动的第一指令。并且，当执行两个或更多个测试的附加测试时，提供再次使用测试环境的组件的第二指令，从而避免执行重复的设置活动。

7. 发明申请

US20120246604A1 COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL 失效
标题翻译：计算机辅助设计系统，用于自动扫描合成记录级别
公开(公告)号：US20120246604A1
公开(公告)日：2012-09-27
申请号：US13490721
申请日：2012-06-07
申请人： Laung-Terng (L. -T.) WANG , Augusli Kifli , Fei-Sheng Hsu , Shih-Chia Kao , Xiaoqing Wen , Shyh-Horag Lin , Hsin-Po Wang
发明人： Laung-Terng (L. -T.) WANG , Augusli Kifli , Fei-Sheng Hsu , Shih-Chia Kao , Xiaoqing Wen , Shyh-Horag Lin , Hsin-Po Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31704 , G01R31/318314 , G01R31/318364 , G01R31/318583 , G01R31/318594 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F2217/14
摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
摘要翻译：一种在寄存器传输级（RTL）下自动扫描合成的方法和系统。该方法和系统将产生在RTL建模的扫描HDL代码，用于在RTL建模的集成电路。该方法和系统包括执行RTL可测试性分析，时钟域最小化，扫描选择，测试点选择，扫描修复和测试点插入，扫描替换和扫描拼接，扫描提取，交互式扫描调试，交互式扫描修复的计算机实现步骤和冲洗/随机测试台生成。此外，本发明还包括通过逐个模块执行扫描合成然后将这些扫描的模块拼接在一起的层次扫描合成的方法和系统。本发明还包括将扫描HDL码与其他测试（DFT）HDL码进行集成和验证，包括边界扫描和逻辑BIST（内置自检）。

8. 发明授权

US08135558B2 Automated simulation testbench generation for serializer/deserializer datapath systems 有权
标题翻译：串行器/解串器数据路径系统的自动仿真测试平台生成
公开(公告)号：US08135558B2
公开(公告)日：2012-03-13
申请号：US12169668
申请日：2008-07-09
申请人： Francis A. Kampf , Jeanne Trinko-Mechler , David R. Stauffer
发明人： Francis A. Kampf , Jeanne Trinko-Mechler , David R. Stauffer
IPC分类号： G06F11/00 , G06F19/00
CPC分类号： G06F17/5022 , G01R31/318314
摘要： Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.
摘要翻译：本文的实施例提供了一种用于串行器/解串器数据路径系统的自动化仿真测试台生成的方法。该方法提供用于生成和检查数据路径系统内的数据的事务处理器的数据库，其中事务处理器适用于数据通路系统的任意配置。数据库提供了每个核心单个事务处理器集合。接下来，该方法自动从数据库中选择一组事务处理器，以便包含在仿真测试台中。接下来，该方法通过将所选择的一组事务处理器与数据路径系统相互连接，通过数据路径系统映射第一个数据路径和第二个数据路径。该方法还包括设置核上的控制引脚以便于数据通过数据路径系统的核心的传播。随后，控制引脚被跟踪到输入端口和控制寄存器。

9. 发明授权

US08082541B2 Method and system for performing installation and configuration management of tester instrument modules 失效
标题翻译：用于执行测试仪器模块的安装和配置管理的方法和系统
公开(公告)号：US08082541B2
公开(公告)日：2011-12-20
申请号：US11100109
申请日：2005-04-05
申请人： Ankan Pramanick , Jim Hanrahan , Mark Elston , Toshiaki Adachi , Leon L. Chen
发明人： Ankan Pramanick , Jim Hanrahan , Mark Elston , Toshiaki Adachi , Leon L. Chen
IPC分类号： G06F9/44 , G06F9/45 , G06F9/445
CPC分类号： G06F9/44 , G01R31/3183 , G01R31/318307 , G01R31/318314 , G01R31/319 , G01R31/31907 , G01R31/31908 , G06F8/61
摘要： A method for managing multiple hardware test module versions, software components, and tester operating system (TOS) versions in a modular test system is disclosed. The method includes installing the TOS versions compatible with the modular test system in an archive and installing vendor software components corresponding to the hardware test module versions in the archive. The method further includes creating system profiles for describing vendor software components corresponding to the hardware test module versions and the TOS versions, selecting a system profile for the modular test system, where the system profile includes a set of compatible vendor software components and a selected TOS for testing a particular hardware test module version, and activating the selected TOS on the modular test system.
摘要翻译：公开了一种在模块化测试系统中管理多个硬件测试模块版本，软件组件和测试仪操作系统（TOS）版本的方法。该方法包括将与模块化测试系统兼容的TOS版本安装在归档中，并安装与存档中的硬件测试模块版本对应的供应商软件组件。该方法还包括创建用于描述对应于硬件测试模块版本和TOS版本的供应商软件组件的系统简档，为模块化测试系统选择系统简档，其中系统简档包括一组兼容供应商软件组件和选择的TOS 用于测试特定硬件测试模块版本，并激活模块化测试系统上选定的TOS。

10. 发明授权

US08069130B2 Methods and systems for semiconductor testing using a testing scenario language 有权
标题翻译：使用测试场景语言进行半导体测试的方法和系统
公开(公告)号：US08069130B2
公开(公告)日：2011-11-29
申请号：US12493460
申请日：2009-06-29
申请人： Gil Balog
发明人： Gil Balog
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G01R31/31912 , G01R31/318314 , G06N5/025
摘要： Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs.
摘要翻译：半导体测试方法和系统。在一个实施例中，半导体测试方法包括以下阶段中的一个或多个：定义与半导体测试有关的规则，验证规则，将规则与其他规则绑定，将规则与其他规则相关联，发布规则，实现规则，并对有关规则采取后续行动。在一个实施例中，半导体测试系统包括以下模块中的一个或多个：规则创建模块，分析模块，模拟模块，实时生产模块和离线生产模块）。在一个实施例中，用户友好的图形用户界面可用于定义规则的构建块和/或用于查看规则所属的类别的可选层次结构。

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