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1. 发明申请

US20080195920A1 SELF-TEST STRUCTURE AND METHOD OF TESTING A DIGITAL INTERFACE 审中-公开
标题翻译：自测试结构和测试数字接口的方法
公开(公告)号：US20080195920A1
公开(公告)日：2008-08-14
申请号：US11674478
申请日：2007-02-13
申请人： Lawrence B. Luce , Paul Kelleher , Diarmuid McSwiney
发明人： Lawrence B. Luce , Paul Kelleher , Diarmuid McSwiney
IPC分类号： G06F11/00 , H04B17/00
CPC分类号： G01R31/31716
摘要： A digital interface (22) includes a self-test structure (56). The structure (56) includes a transmit section (52) and a receive section (36) having a correlator (68). A method (114) of testing the interface (22) entails coupling the receive section (36) with the transmit section (52) and communicating a test data structure (86) from the transmit section (52) to the receive section (36) at a high data rate. The test data structure (86) includes a pre-defined sync pattern (88), a header (90), and a payload (92). The receive section (36) detects the sync pattern (88) and performs time frame synchronization (148) at the correlator (68). When synchronization (148) is successful, the receive section (36) decodes (154, 162) the header (90) and the payload (92). If time frame synchronization (148) and decoding (154, 162) are successful, a validation indicator (100) is output for external observation at a low data rate.
摘要翻译：数字接口（22）包括自检结构（56）。结构（56）包括具有相关器（68）的发射部分（52）和接收部分（36）。测试接口（22）的方法（114）需要将接收部分（36）与发送部分（52）耦合并将测试数据结构（86）从发送部分（52）传送到接收部分（36）以高数据速率。测试数据结构（86）包括预定义同步模式（88），报头（90）和有效载荷（92）。接收部分（36）检测同步模式（88）并且在相关器（68）处执行时间帧同步（148）。当同步（148）成功时，接收部分（36）解码（154,162）标题（90）和有效载荷（92）。如果时间帧同步（148）和解码（154,162）成功，则以低数据速率输出验证指示符（100）以进行外部观察。

2. 发明授权

US08391415B2 Electronic device, integrated circuit and method for selecting of an optimal sampling clock phase 有权
标题翻译：电子设备，集成电路和选择最佳采样时钟相位的方法
公开(公告)号：US08391415B2
公开(公告)日：2013-03-05
申请号：US12522047
申请日：2007-01-09
申请人： Paul Kelleher , Diarmuid McSwiney , Conor O'Keeffe
发明人： Paul Kelleher , Diarmuid McSwiney , Conor O'Keeffe
IPC分类号： H03K9/00
CPC分类号： H04L7/042 , H04B1/005 , H04B1/70753 , H04L7/0337
摘要： An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.
摘要翻译：电子设备包括通过接口耦合的多个子系统。子系统中的一个包括用于接收在相应数据路径上具有多个相位的输入数据帧的逻辑。电子设备还包括用于以可选择地耦合到选择逻辑的预定比特模式对所接收的输入数据执行互相关的逻辑，用于从发送到接口的多个相位中选择单相以对接收到的输入数据进行采样响应于互相关的数据位周期的中间区域。

3. 发明申请

US20100111154A1 ELECTRONIC DEVICE, INTEGRATED CIRCUIT AND METHOD THEREFOR 有权
标题翻译：电子设备，集成电路及其方法
公开(公告)号：US20100111154A1
公开(公告)日：2010-05-06
申请号：US12522043
申请日：2007-01-09
申请人： Paul Kelleher , Diarmuid McSwiney , Conor O'Keeffe , Emilio Quiroga , Samir Soni
发明人： Paul Kelleher , Diarmuid McSwiney , Conor O'Keeffe , Emilio Quiroga , Samir Soni
IPC分类号： H04L27/00 , H04B17/00
CPC分类号： H04L7/0338 , H04L7/042
摘要： A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.
摘要翻译：无线通信设备包括多个子系统和时钟生成逻辑，其布置成生成要应用于子系统数量的至少一个时钟信号。子系统的数量之一包括用于接收输入数据的采样逻辑，并且使用施加到采样逻辑的至少一个时钟信号的时钟周期的多个分离相位对输入数据位执行初始采样，从而产生多相分离采样输入数据位的输出。采样逻辑被配置为在多个中间相位的多相分离采样输出上执行多个重采样操作，从而在执行多相分离中间采样输出的最终采样之前产生多相分离中间采样输出所述至少一个时钟信号的单相以产生采样的输入数据信号。

4. 发明授权

US08306172B2 Electronic device, integrated circuit and method therefor 有权
标题翻译：电子设备，集成电路及其方法
公开(公告)号：US08306172B2
公开(公告)日：2012-11-06
申请号：US12522043
申请日：2007-01-09
申请人： Paul Kelleher , Diarmuid McSwiney , Conor O'Keeffe , Emilio Quiroga , Samir Soni
发明人： Paul Kelleher , Diarmuid McSwiney , Conor O'Keeffe , Emilio Quiroga , Samir Soni
IPC分类号： H04L7/00
CPC分类号： H04L7/0338 , H04L7/042
摘要： A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.
摘要翻译：无线通信设备包括多个子系统和时钟生成逻辑，其布置成生成要应用于子系统数量的至少一个时钟信号。子系统的数量之一包括用于接收输入数据的采样逻辑，并且使用施加到采样逻辑的至少一个时钟信号的时钟周期的多个分离相位对输入数据位执行初始采样，从而产生多相分离采样输入数据位的输出。采样逻辑被配置为在多个中间相位的多相分离采样输出上执行多个重采样操作，从而在执行多相分离中间采样输出的最终采样之前产生多相分离中间采样输出所述至少一个时钟信号的单相以产生采样的输入数据信号。

5. 发明申请

US20110142169A1 ELECTRONIC DEVICE, INTEGRATED CIRCUIT AND METHOD FOR SELECTING OF AN OPTIMAL SAMPLING CLOCK PHASE 有权
标题翻译：电子设备，集成电路和选择最佳采样时钟相位的方法
公开(公告)号：US20110142169A1
公开(公告)日：2011-06-16
申请号：US12522047
申请日：2007-01-09
申请人： Paul Kelleher , Diarmuid McSwiney , Conor O'keeffe
发明人： Paul Kelleher , Diarmuid McSwiney , Conor O'keeffe
IPC分类号： H04L27/00
CPC分类号： H04L7/042 , H04B1/005 , H04B1/70753 , H04L7/0337
摘要： An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.
摘要翻译：电子设备包括通过接口耦合的多个子系统。子系统中的一个包括用于接收在相应数据路径上具有多个相位的输入数据帧的逻辑。电子设备还包括用于以可选择地耦合到选择逻辑的预定比特模式对所接收的输入数据执行互相关的逻辑，用于从发送到接口的多个相位中选择单相以对接收到的输入数据进行采样响应于互相关的数据位周期的中间区域。

6. 发明申请

US20100048239A1 COMMUNICATION DEVICE, INTEGRATED CIRCUIT AND METHOD THEREFOR 有权
标题翻译：通信设备，集成电路及其方法
公开(公告)号：US20100048239A1
公开(公告)日：2010-02-25
申请号：US12522045
申请日：2007-01-11
申请人： Paul Kelleher , Patrick Gayer , Diarmuid McSwiney
发明人： Paul Kelleher , Patrick Gayer , Diarmuid McSwiney
IPC分类号： H04M1/00
CPC分类号： H04W52/0241 , H04J3/0697 , H04L7/042 , H04W88/06 , Y02D70/122 , Y02D70/124 , Y02D70/144
摘要： A communication device is capable of supporting communication compliant with a Dual-Mode 2.5G and 3G interface baseband-radio frequency interface standard and comprises a data interface operably coupled to a number sub-systems and a clock circuit generating a plurality of clock phases for supporting communication there between. At least one of the number of sub-systems comprises a line driver and a line receiver; wherein the communication device is characterised in that the line receiver determines an end of a received data frame sent across the data interface and in response thereto switches itself off.
摘要翻译：通信设备能够支持符合双模2.5G和3G接口基带射频接口标准的通信，并且包括可操作地耦合到多个子系统的数据接口和产生多个时钟相位的时钟电路，用于支持沟通之间。多个子系统中的至少一个包括线路驱动器和线路接收器; 其中所述通信设备的特征在于，所述线路接收机确定在所述数据接口上发送的接收数据帧的结束，并响应于所述接收数据帧切换自身。

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