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1. 发明申请

US20210328057A1 THREE DIMENSIONAL VERTICALLY STRUCTURED ELECTRONIC DEVICES 有权
公开(公告)号：US20210328057A1
公开(公告)日：2021-10-21
申请号：US17238012
申请日：2021-04-22
申请人： Lawrence Livermore National Security, LLC
发明人： Adam Conway , Sara Elizabeth Harrison , Rebecca Nikolic , Qinghui Shao , Lars Voss
IPC分类号： H01L29/78 , H01L29/778 , H01L29/20 , H01L29/205 , H01L29/808 , H01L29/66 , H01L29/06
摘要： An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.

2. 发明申请

US20190393038A1 GALLIDATION ASSISTED IMPURITY DOPING 审中-公开
公开(公告)号：US20190393038A1
公开(公告)日：2019-12-26
申请号：US16446460
申请日：2019-06-19
申请人： Lawrence Livermore National Security, LLC
发明人： Lars Voss , Daniel Max Dryden , Clint Frye , Sara Elizabeth Harrison , Rebecca J. Nikolic , Qinghui Shao
IPC分类号： H01L21/225 , H01L29/20 , H01L29/207 , H01L21/324
摘要： In one embodiment, a product includes a structure comprising a material of a Group-III-nitride having a dopant, where a concentration of the dopant in the structure has a concentration gradient characteristic of diffusion of the dopant inward from at least a portion of a surface of the structure in a direction substantially normal to the portion of the surface. The structure has less than 1% decomposition of the Group-III-nitride at the surface of the structure.

3. 发明申请

US20180145187A1 LIQUID SEMICONDUCTOR-HALOGEN BASED ELECTRONICS 审中-公开
公开(公告)号：US20180145187A1
公开(公告)日：2018-05-24
申请号：US15812682
申请日：2017-11-14
申请人： Lawrence Livermore National Security, LLC
发明人： Lars Voss , Clint Frye , Roger A. Henderson , John Winter Murphy , Rebecca J. Nikolic , Dongxia Qu , Qinghui Shao , Mark A. Stoyer
IPC分类号： H01L29/872 , H01L29/18 , H01L29/24 , H01L23/31
CPC分类号： H01L29/872 , G21H1/06 , H01L23/3107 , H01L29/18 , H01L29/24 , H01L29/267 , H01L29/861 , H01L31/0272 , H01L31/02725 , H01L31/03044 , H01L31/072
摘要： According to one embodiment, a device includes a first electrode, a second electrode spaced from the first electrode, a well extending between the first electrode and the second electrode, one or more chalcogens in the well, and at least one halogen mixed with the one or more chalcogens in the well. In addition, the chalcogens are selected from the group consisting of sulfur, selenium, tellurium, and polonium.

4. 发明申请

US20170200820A1 THREE DIMENSIONAL VERTICALLY STRUCTURED ELECTRONIC DEVICES 审中-公开
公开(公告)号：US20170200820A1
公开(公告)日：2017-07-13
申请号：US14990612
申请日：2016-01-07
申请人： Lawrence Livermore National Security, LLC
发明人： Adam Conway , Sara Elizabeth Harrison , Rebecca Nikolic , Qinghui Shao , Lars Voss
IPC分类号： H01L29/778 , H01L29/10 , H01L29/205 , H01L29/66 , H01L29/20
CPC分类号： H01L29/7827 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/66924 , H01L29/7788 , H01L29/7789 , H01L29/8083
摘要： According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

5. 发明申请

US20190259903A1 THREE-DIMENSIONAL CO-AXIAL LINEAR PHOTONIC SWITCH 审中-公开
公开(公告)号：US20190259903A1
公开(公告)日：2019-08-22
申请号：US16401016
申请日：2019-05-01
申请人： Lawrence Livermore National Security, LLC
发明人： Adam Conway , Mihail Bora , Paulius Vytautas Grivickas , Lars Voss
IPC分类号： H01L31/16 , H03K17/78 , H01L31/0224
摘要： Techniques, systems, and devices are disclosed that relate to coaxial photoconductive switch modules. The coaxial photoconductive switch may include an outer conductor, an inner conductor, and a photoconductive material positioned between the inner conductor and the outer conductor. The inner conductor, the outer conductor, and the photoconductive material have a predetermined height. A bias voltage may be applied between the inner conductor and the outer conductor. When light of a predetermined wavelength and a predetermined intensity is incident on the photoconductive material, the photoconductive material may break down allowing a current to flow through the photoconductive material between the inner conductor and the outer conductor.

6. 发明申请

US20170222047A1 THREE DIMENSIONAL VERTICALLY STRUCTURED ELECTRONIC DEVICES 审中-公开
公开(公告)号：US20170222047A1
公开(公告)日：2017-08-03
申请号：US15398652
申请日：2017-01-04
申请人： Lawrence Livermore National Security, LLC
发明人： Adam Conway , Sara Elizabeth Harrison , Rebecca J. Nikolic , Qinghui Shao , Lars Voss
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/205 , H01L29/20
CPC分类号： H01L29/7827 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/66924 , H01L29/7788 , H01L29/7789 , H01L29/8083
摘要： In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

7. 发明授权

US09645262B2 Capacitance reduction for pillar structured devices 有权
公开(公告)号：US09645262B2
公开(公告)日：2017-05-09
申请号：US14555463
申请日：2014-11-26
申请人： Lawrence Livermore National Security, LLC
发明人： Qinghui Shao , Adam Conway , Rebecca J. Nikolic , Lars Voss , Ishwara B. Bhat , Sara E. Harrison
IPC分类号： G01T3/00 , G01T3/08 , H01L31/117
CPC分类号： G01T3/08 , H01L31/115 , H01L31/117
摘要： In one embodiment, an apparatus includes: a first layer including a n+ dopant or p+ dopant; an intrinsic layer formed above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, cavity regions being defined between the pillars; and a second layer deposited on a periphery of the pillars thereby forming coated pillars, the second layer being substantially absent on the planar portion of the intrinsic layer between the coated pillars. The second layer includes an n+ dopant when the first layer includes a p+ dopant. The second layer includes a p+ dopant when the first layer includes an n+ dopant. The apparatus includes a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer. In additional embodiments, an upper portion of each of the pillars includes a same type of dopant as the second layer.

8. 发明申请

US20130334541A1 THREE DIMENSIONAL STRAINED SEMICONDUCTORS 有权
标题翻译：三维应变半导体
公开(公告)号：US20130334541A1
公开(公告)日：2013-12-19
申请号：US13912885
申请日：2013-06-07
申请人： Lawrence Livermore National Security, LLC
发明人： Lars Voss , Adam Conway , Rebecca J. Nikolic , Cedric Rocha Leao , Qinghui Shao
IPC分类号： H01L29/06 , H01L21/02
CPC分类号： H01L29/0657 , H01L21/02107 , H01L27/1021 , H01L29/861
摘要： In one embodiment, an apparatus includes a three dimensional structure comprising a semiconductor material, and at least one thin film in contact with at least one exterior surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the three dimensional structure. In another embodiment, a method includes forming a three dimensional structure comprising a semiconductor material, and depositing at least one thin film on at least one surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the structure.
摘要翻译：在一个实施例中，一种装置包括三维结构，其包括半导体材料，以及至少一个与所述三维结构的至少一个外表面接触的薄膜，用于在所述结构中引起应变，所述薄膜的特征在于提供至少一种：至少0.05％的诱导应变，以及在至少5％体积的三维结构中的诱导应变。在另一个实施例中，一种方法包括形成包括半导体材料的三维结构，以及在三维结构的至少一个表面上沉积至少一个薄膜，用于在结构中引起应变，该薄膜的特征在于提供至少一种：至少0.05％的诱导应变，以及至少5％体积结构的诱导应变。

9. 发明授权

US11024734B2 Three dimensional vertically structured electronic devices 有权
公开(公告)号：US11024734B2
公开(公告)日：2021-06-01
申请号：US15398652
申请日：2017-01-04
申请人： Lawrence Livermore National Security, LLC
发明人： Adam Conway , Sara Elizabeth Harrison , Rebecca J. Nikolic , Qinghui Shao , Lars Voss
IPC分类号： H01L29/78 , H01L29/778 , H01L29/20 , H01L29/205 , H01L29/808 , H01L29/66 , H01L29/06
摘要： In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

10. 发明授权

US11018253B2 Three dimensional vertically structured electronic devices 有权
公开(公告)号：US11018253B2
公开(公告)日：2021-05-25
申请号：US14990612
申请日：2016-01-07
申请人： Lawrence Livermore National Security, LLC
发明人： Adam Conway , Sara Elizabeth Harrison , Rebecca Nikolic , Qinghui Shao , Lars Voss
IPC分类号： H01L29/78 , H01L29/778 , H01L29/20 , H01L29/205 , H01L29/808 , H01L29/66 , H01L29/06
摘要： According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

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