专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08391367B1 High performance context-adaptive video processor 有权
标题翻译：高性能上下文自适应视频处理器
公开(公告)号：US08391367B1
公开(公告)日：2013-03-05
申请号：US12645740
申请日：2009-12-23
申请人： Leslie D. Kohn , Ellen M. Lee , Benghan Lui
发明人： Leslie D. Kohn , Ellen M. Lee , Benghan Lui
IPC分类号： H04N11/02
CPC分类号： H04N19/436 , H04N19/13 , H04N19/42
摘要： An apparatus comprising a transform circuit, a first coder circuit, a second coder circuit, and a memory circuit. The transform circuit may be configured to generate (i) one or more first coefficients in response to a sample signal when in a first mode and (ii) the sample signal in response to the first coefficients when in a second mode. The first coder circuit may be configured to generate (i) a first bitstream signal in response to one or more second coefficients when in the first mode and (ii) the second coefficients in response to the first bitstream signal when in the second mode. The second coder circuit may be configured to generate (i) a second bitstream signal in response to one or more third coefficients when in the first mode and (ii) the third coefficients in response to the second bitstream signal when in the second mode. The memory circuit may be configured to store the first coefficients, the second coefficients, and the third coefficients. The memory may be configured to allow the transform circuit, the first coder circuit, and the second coder circuit to operate independently.
摘要翻译：一种包括变换电路，第一编码器电路，第二编码器电路和存储器电路的装置。变换电路可以被配置为当处于第一模式时响应于采样信号产生（i）一个或多个第一系数，以及（ii）当处于第二模式时响应于第一系数的采样信号。第一编码器电路可以被配置为当处于第一模式时响应于一个或多个第二系数而产生（i）第一比特流信号，以及（ii）当处于第二模式时，响应于第一比特流信号的第二系数。第二编码器电路可以被配置为当处于第一模式时响应于一个或多个第三系数而产生（i）第二比特流信号，以及当处于第二模式时响应于第二比特流信号的第三系数。存储器电路可以被配置为存储第一系数，第二系数和第三系数。存储器可以被配置为允许变换电路，第一编码器电路和第二编码器电路独立地操作。

2. 发明授权

US09378561B1 Layer switching in an H.264 scalable video decoder 有权
标题翻译： H.264可分级视频解码器中的层交换
公开(公告)号：US09378561B1
公开(公告)日：2016-06-28
申请号：US12796042
申请日：2010-06-08
申请人： Leslie D. Kohn , Ellen M. Lee , Peter Verplaetse
发明人： Leslie D. Kohn , Ellen M. Lee , Peter Verplaetse
IPC分类号： G06T9/00
CPC分类号： G06T9/004 , H04N19/33 , H04N19/423 , H04N19/44 , H04N19/61 , H04N19/91
摘要： An apparatus comprising a decoder circuit, a memory circuit and a processing circuit. The decoder circuit may be configured to generate a first intermediate signal having a plurality of coefficients of a target layer and a plurality of coefficients of a base layer, in response to an input bitstream. The memory circuit may be configured to (i) store the first intermediate signal and (ii) present (a) a second intermediate signal comprising the plurality of coefficients of the target layer or (b) a third intermediate signal comprising the plurality of coefficients of the base layer. The processing circuit may be configured to (i) switch a plurality of times between the coefficients of the target layer and the coefficients of the base layer while reading a frame from the memory circuit, (ii) transform the coefficients of the base layer into base layer information, (iii) buffer the base layer information, where the base layer information buffered at any time comprises at most a subset of macroblock rows of the frame and (iv) generate an output signal comprising a plurality of target layer samples in response to the second intermediate signal and the base layer information as buffered.
摘要翻译：一种包括解码器电路，存储器电路和处理电路的装置。解码器电路可以被配置为响应于输入比特流而生成具有目标层的多个系数和基本层的多个系数的第一中间信号。存储器电路可以被配置为（i）存储第一中间信号和（ii）存在（a）包括目标层的多个系数的第二中间信号或（b）第三中间信号，包括多个系数的基层。处理电路可以被配置为（i）在从存储器电路读取帧的同时，在目标层的系数和基本层的系数之间切换多次，（ii）将基本层的系数转换为基础层信息，（iii）缓冲基层信息，其中在任何时间缓存的基层信息最多包括该帧的宏块行的一个子集，以及（iv）响应于该层信息生成包含多个目标层样本的输出信号第二中间信号和基本层信息被缓冲。

3. 发明授权

US08694755B1 Virtual memory management for real-time embedded devices 有权
标题翻译：用于实时嵌入式设备的虚拟内存管理
公开(公告)号：US08694755B1
公开(公告)日：2014-04-08
申请号：US12725899
申请日：2010-03-17
申请人： Kathirgamar Aingaran , Leslie D. Kohn , Robert C. Kunz , Jenn-Yuan Tsai
发明人： Kathirgamar Aingaran , Leslie D. Kohn , Robert C. Kunz , Jenn-Yuan Tsai
IPC分类号： G06F12/10
CPC分类号： G06F12/0284 , G06F12/10 , G06F12/1009 , G06F12/1027 , G06F2212/651
摘要： An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.
摘要翻译：一种包括调节器电路，平移电路和控制器电路的装置。仲裁器电路可以被配置为响应于输入信号和读取数据信号而产生一个或多个第一控制信号和数据写入信号。翻译电路可以被配置为响应于一个或多个第一控制信号和写入地址信号而产生一个或多个第二控制信号。控制器电路可以被配置为响应于一个或多个第二控制信号而产生地址信号。

4. 发明授权

US08531549B1 Camera that uses YUV to YUV table-based color correction for processing digital images 有权
标题翻译：相机使用YUV到YUV基于表的颜色校正来处理数字图像
公开(公告)号：US08531549B1
公开(公告)日：2013-09-10
申请号：US12712307
申请日：2010-02-25
申请人： Elliot N. Linzer , Leslie D. Kohn
发明人： Elliot N. Linzer , Leslie D. Kohn
IPC分类号： H04N9/73
CPC分类号： H04N9/68 , H04N9/045 , H04N9/67
摘要： An apparatus having a circuit is disclosed. The circuit may be configured to (i) process a digital image received from a camera sensor and (ii) color correct at least one pixel of the digital image after the processing. The color correction generally includes a lookup table-based conversion of the pixel from a first luminance-and-chrominance representation to a second luminance-and-chrominance representation.
摘要翻译：公开了一种具有电路的装置。电路可以被配置为（i）处理从相机传感器接收的数字图像，以及（ii）在处理之后对数字图像的至少一个像素进行颜色校正。颜色校正通常包括将像素从第一亮度和色度表示到第二亮度和色度表示的基于查找表的转换。

5. 发明授权

US08498338B1 Mode decision using approximate ½ pel interpolation 有权
标题翻译：使用近似½贝尔插值的模式决策
公开(公告)号：US08498338B1
公开(公告)日：2013-07-30
申请号：US13585091
申请日：2012-08-14
申请人： Shih-Hao Wang , Leslie D. Kohn , Tihao Chiang
发明人： Shih-Hao Wang , Leslie D. Kohn , Tihao Chiang
IPC分类号： H04N7/12
CPC分类号： H04N19/523 , H04N19/103 , H04N19/117 , H04N19/61 , H04N19/82
摘要： A method for video encoding is disclosed. The method generally includes the steps of (A) generating first sub-pel data for at least one of (i) a motion estimation and (ii) a mode decision by first filtering reference data and (B) generating second sub-pel data for a motion compensation by second filtering the reference data. Wherein a first performance of the first filtering may be different than a second performance of the second filtering.
摘要翻译：公开了一种用于视频编码的方法。该方法通常包括以下步骤：（A）为（i）运动估计和（ii）通过首先过滤参考数据的模式决定和（B）生成第二子像素数据中的至少一个生成第一子像素数据，通过对参考数据进行二次过滤来进行运动补偿。其中，第一过滤的第一性能可以不同于第二过滤的第二性能。

6. 发明授权

US07865667B2 Multi-core multi-thread processor 有权
标题翻译：多核多线程处理器
公开(公告)号：US07865667B2
公开(公告)日：2011-01-04
申请号：US11686317
申请日：2007-03-14
申请人： Leslie D. Kohn , KunIe A. Olukotun , Michael K. Wong
发明人： Leslie D. Kohn , KunIe A. Olukotun , Michael K. Wong
IPC分类号： G06F13/00
CPC分类号： H04L47/10 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/1423 , G06F9/30007 , G06F9/30043 , G06F9/3851 , G06F9/3879 , G06F9/3891 , G06F11/108 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F13/1689 , G06F21/72 , G09G2352/00 , G09G2360/121 , G09G2370/022 , G09G2370/20 , G11C11/4074 , H04L29/06 , H04L45/745 , H04L47/2441 , H04L49/90 , H04L49/9057 , H04L49/9089 , H04L69/22 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.
摘要翻译：在一个实施例中，提供处理器。处理器包括至少两个核，其中每个核包括第一级高速缓冲存储器。每个核心都是多线程的。在另一个实施例中，每个芯包括四个螺纹。在另一个实施例中，包括交叉开关。提供了通过横杆与内核通信的多个缓存组存储器。多个高速缓存组存储器中的每一个与主存储器接口通信。在另一个实施例中，还包括与多个高速缓存组存储器中的每一个通信的缓冲器开关核心。还提供了用于优化多线程处理器核的利用率的服务器和方法。

7. 发明授权

US5727219A Virtual input/output processor utilizing an interrupt handler 失效
标题翻译：虚拟输入/输出处理器利用中断处理程序
公开(公告)号：US5727219A
公开(公告)日：1998-03-10
申请号：US854113
申请日：1997-05-09
申请人： Thomas L. Lyon , Sun-Den Chen , William Joy , Leslie D. Kohn , Charles E. Narad , Robert Yung
发明人： Thomas L. Lyon , Sun-Den Chen , William Joy , Leslie D. Kohn , Charles E. Narad , Robert Yung
IPC分类号： G06F13/10 , G06F13/28 , G06F13/38 , G06F9/46 , G06F13/24
CPC分类号： G06F13/28 , G06F13/10 , G06F13/385
摘要： A virtual I/O processor (VIOP) is implemented using a programmed I/O (PIO) unit. The PIO unit is complemented by a VIOP interrupt, a VIOP interrupt handler, and a number of VIOP data structures. Preferably, the PIO unit is further complemented with a set of dedicated I/O global registers, a number of VIOP library read/write routines for various I/O device types, and non-blocking read and write operations. During execution, these elements cooperate with each other to perform multiple sequences of programmed I/Os as if they were being performed by a dedicated I/O processor.
摘要翻译：使用编程的I / O（PIO）单元实现虚拟I / O处理器（VIOP）。 PIO单元由VIOP中断，VIOP中断处理程序和多个VIOP数据结构补充。优选地，PIO单元进一步补充有一组专用I / O全局寄存器，用于各种I / O设备类型的多个VIOP库读/写例程以及非阻塞读写操作。在执行期间，这些元件彼此协作以执行多个编程I / O序列，就像它们由专用I / O处理器执行一样。

8. 发明授权

US5265227A Parallel protection checking in an address translation look-aside buffer 失效
标题翻译：地址转换后备缓冲区中的并行保护检查
公开(公告)号：US5265227A
公开(公告)日：1993-11-23
申请号：US853008
申请日：1992-03-17
申请人： Leslie D. Kohn , Shai Rotem
发明人： Leslie D. Kohn , Shai Rotem
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/1027
摘要： A translation look-aside buffer is implemented utilizing a four-way set associative cache memory having four lines of 16 sets each. A virtual address tag and its corresponding physical address tag, as well as a number of status bits which control the type of access permitted for a given virtual address, are stored in the translation look-aside buffer. A portion of the inputted virtual address signal is used to provide a virtual address tag and is compared to the virtual address tag in the buffer memory. When the virtual address tag comparison is achieved, the physical address tags are provided as an output from the translation look-aside buffer. Also at the same time, a fault detection circuit performs various fault detection logic on the status bits, depending on the execution cycle being performed, such as read/write cycle or user/supervisor mode. If a hit occurs with one of the stored virtual address tags, its physical address tag is used, but only if a fault indication does not occur thereby generating a trap. The comparison of the virtual address tags, the generation of the physical address tag and checking of the status bits for fault detection is performed simultaneously in parallel so that only one clock cycle is needed to generate a physical address tag and a fault signal, if any, from the address translation look-aside buffer.
摘要翻译：使用具有四行每组16组的四路组关联高速缓冲存储器来实现翻译后备缓冲器。虚拟地址标签及其对应的物理地址标签以及控制给定虚拟地址所允许的访问类型的多个状态位存储在翻译后备缓冲器中。输入的虚拟地址信号的一部分用于提供虚拟地址标签，并将其与缓冲存储器中的虚拟地址标签进行比较。当实现虚拟地址标签比较时，物理地址标签被提供为来自翻译后备缓冲器的输出。同时，故障检测电路根据所执行的执行周期，例如读/写周期或用户/管理员模式，对状态位执行各种故障检测逻辑。如果使用其中一个存储的虚拟地址标签发生命中，则使用其物理地址标记，但只有当不发生故障指示从而产生陷阱时。虚拟地址标签的比较，物理地址标签的生成和故障检测的状态位的检查是并行执行的，因此只需要一个时钟周期来生成物理地址标签和故障信号（如果有的话），从地址转换后备缓冲区。

9. 发明授权

US5241636A Method for parallel instruction execution in a computer 失效
标题翻译：计算机中并行指令执行的方法
公开(公告)号：US5241636A
公开(公告)日：1993-08-31
申请号：US479946
申请日：1990-02-14
申请人： Leslie D. Kohn
发明人： Leslie D. Kohn
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3853 , G06F9/3885
摘要： A method for parallel instruction execution in a computer is described. If the computer is executing in the single-instruction mode and the computer encounters a first type of instruction with a dual-instruction mode bit having a first value, then one more single instruction is executed before dual-instruction mode instruction execution begins. The first type of instruction is an instruction having a dual-instruction mode bit. The dual-instruction mode instruction execution occurs in parallel. If the computer is executing in the dual-instruction mode and the computer encounters the first type of instruction with the dual-instruction mode bit having a second value, wherein the second value is different from the first value, then one more dual instruction is executed before single-instruction mode instruction execution resumes.
摘要翻译：描述了计算机中并行指令执行的方法。如果计算机以单指令模式执行，并且计算机遇到具有第一值的双指令模式位的第一类指令，则在双指令模式指令执行开始之前执行再一个单指令。第一类指令是具有双指令模式位的指令。双指令模式指令执行并行执行。如果计算机以双指令模式执行，并且计算机遇到具有第二值的双指令模式位的第一类型的指令，其中第二值不同于第一值，则再执行一个双指令在单指令模式指令执行恢复之前。

10. 发明授权

US5155816A Pipelined apparatus and method for controlled loading of floating point data in a microprocessor 失效
标题翻译：用于在微处理器中控制加载浮点数据的流水线装置和方法
公开(公告)号：US5155816A
公开(公告)日：1992-10-13
申请号：US742289
申请日：1991-08-08
申请人： Leslie D. Kohn
发明人： Leslie D. Kohn
IPC分类号： G06F9/312 , G06F9/38 , G06F15/78
CPC分类号： G06F9/30043 , G06F15/8069 , G06F9/383 , G06F9/3875
摘要： A microprocessor having a pipelined architecture, an onchip data cache, a floating-point unit, a floating-point data latch and an instruction for accessing infrequently used data from an external memory system is disclosed. The instruction comprises a first-in-first-out memory for accumulating data in a pipeline manner, a first circuit means for coupling data from the external bus to the first-in-first-out memory and a second circuit means for transferring the data stored in the first-in-first-out memory to the floating-point data latch. The second circuit means also couples data from the cache to the first-in-first-out memory in the event of a cache hit. Finally, a bus control means is provided for controlling the orderly flow of data in accordance with the architecture of the microprocessor.
摘要翻译：公开了一种具有流水线架构的微处理器，片上数据高速缓存，浮点单元，浮点数据锁存器和用于从外部存储器系统访问不经常使用的数据的指令。指令包括用于以流水线方式累积数据的先进先出存储器，用于将来自外部总线的数据耦合到先进先出存储器的第一电路装置和用于传送数据的第二电路装置存储在先进先出存储器中到浮点数据锁存器。在缓存命中的情况下，第二电路意味着还将数据从高速缓存耦合到先进先出存储器。最后，提供总线控制装置，用于根据微处理器的架构来控制数据的有序流动。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式