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1. 发明授权

US10998267B2 Wafer-level chip-size package with redistribution layer 有权
公开(公告)号：US10998267B2
公开(公告)日：2021-05-04
申请号：US15286844
申请日：2016-10-06
申请人： MediaTek Inc.
发明人： Yan-Liang Ji , Ming-Jen Hsiung
IPC分类号： H01L23/528 , H01L23/48 , H01L23/00 , H01L23/31
摘要： A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.

2. 发明授权

US09953954B2 Wafer-level chip-scale package with redistribution layer 有权
公开(公告)号：US09953954B2
公开(公告)日：2018-04-24
申请号：US15274506
申请日：2016-09-23
申请人： MediaTek Inc.
发明人： Yan-Liang Ji , Ming-Jen Hsiung
IPC分类号： H01L23/52 , H01L23/00
CPC分类号： H01L24/94 , H01L23/3114 , H01L23/3192 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0214 , H01L2224/02145 , H01L2224/02166 , H01L2224/02181 , H01L2224/0235 , H01L2224/02351 , H01L2224/0236 , H01L2224/02371 , H01L2224/02381 , H01L2224/03452 , H01L2224/03462 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05082 , H01L2224/05094 , H01L2224/05096 , H01L2224/05569 , H01L2224/05572 , H01L2224/12105 , H01L2224/13024 , H01L2224/13027 , H01L2224/131 , H01L2224/94 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/014
摘要： A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer.

3. 发明申请

US20180240794A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20180240794A1
公开(公告)日：2018-08-23
申请号：US15677190
申请日：2017-08-15
申请人： MEDIATEK Inc.
发明人： Yan-Liang Ji , Cheng-Hua Lin , Chih-Chung Chiu
IPC分类号： H01L27/06 , H01L29/06 , H01L21/8234 , H01L23/528
CPC分类号： H01L27/0629 , H01L21/823475 , H01L21/823481 , H01L23/528 , H01L27/0617 , H01L28/20 , H01L29/0649 , H01L29/665
摘要： A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.

4. 发明申请

US20220181228A1 SEMICONDUCTOR PACKAGE WITH IMPROVED RELIABILITY 有权
公开(公告)号：US20220181228A1
公开(公告)日：2022-06-09
申请号：US17512665
申请日：2021-10-27
申请人： MEDIATEK INC.
发明人： Tien-Chang Chang , Yan-Liang Ji
IPC分类号： H01L23/31 , H01L23/498 , H01L23/00
摘要： A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.

5. 发明授权

US10373949B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US10373949B2
公开(公告)日：2019-08-06
申请号：US15677190
申请日：2017-08-15
申请人： MEDIATEK Inc.
发明人： Yan-Liang Ji , Cheng-Hua Lin , Chih-Chung Chiu
IPC分类号： H01L27/06 , H01L29/06 , H01L23/528 , H01L21/8234 , H01L29/66 , H01L49/02
摘要： A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.

6. 发明授权

US09006825B1 MOS device with isolated drain and method for fabricating the same 有权
标题翻译：具有隔离漏极的MOS器件及其制造方法
公开(公告)号：US09006825B1
公开(公告)日：2015-04-14
申请号：US14039161
申请日：2013-09-27
申请人： MediaTek Inc.
发明人： Puo-Yu Chiang , Yan-Liang Ji
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/266 , H01L29/0646 , H01L29/0653 , H01L29/1083 , H01L29/42368 , H01L29/7835
摘要： A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a second conductivity type; a second well region disposed in a second portion of the semiconductor substrate, overlying the first well region and having the first conductivity type; a third well region disposed in a third portion of the semiconductor substrate, overlying the first well region having the second conductivity type; a fourth well region disposed in a fourth portion of the semiconductor substrate between the first and third well regions, having the first conductivity type; a gate stack formed over the semiconductor substrate; a source region disposed in a portion of the second well region, having the second conductivity type; and a drain region disposed in a portion of the fourth well region, having the second conductivity type.
摘要翻译：具有隔离漏极的MOS器件包括：具有第一导电类型的半导体衬底; 嵌入在半导体衬底的第一部分中的第一阱区，具有第二导电类型; 第二阱区，设置在所述半导体衬底的第二部分中，覆盖所述第一阱区并且具有所述第一导电类型; 设置在半导体衬底的第三部分中的第三阱区，覆盖具有第二导电类型的第一阱区; 第四阱区，设置在具有第一导电类型的第一和第三阱区之间的半导体衬底的第四部分中; 形成在半导体衬底上的栅叠层; 源区域，其设置在所述第二阱区域的具有所述第二导电类型的部分中; 以及设置在具有第二导电类型的第四阱区域的一部分中的漏极区域。

7. 发明授权

US10541328B2 Semiconductor device capable of high-voltage operation 有权
公开(公告)号：US10541328B2
公开(公告)日：2020-01-21
申请号：US16225077
申请日：2018-12-19
申请人： MEDIATEK INC.
发明人： Cheng-Hua Lin , Yan-Liang Ji , Chih-Wen Hsiung
IPC分类号： H01L29/00 , H01L29/78 , H01L29/40 , H01L27/06 , H01L49/02 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/66
摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.

8. 发明申请

US20170047398A1 ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：电子元器件及其制造方法
公开(公告)号：US20170047398A1
公开(公告)日：2017-02-16
申请号：US15206399
申请日：2016-07-11
申请人： MEDIATEK Inc.
发明人： Yan-Liang Ji , Cheng-Hua Lin , Puo-Yu Chiang
IPC分类号： H01L29/06 , H01L21/768 , H01L29/423 , H01L29/36 , H01L23/535
CPC分类号： H01L29/0653 , H01L21/76895 , H01L23/535 , H01L29/36 , H01L29/402 , H01L29/404 , H01L29/42356 , H01L29/7835
摘要： The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.
摘要翻译：电子部件包括半导体基板，第一掺杂区域，第二掺杂区域，栅极结构，电介质层和导电部分。半导体衬底具有上表面。第一掺杂区域嵌入在半导体衬底中。第二掺杂区域嵌入在半导体衬底中。栅极结构形成在上表面上。电介质层形成在上表面上方并位于第一掺杂区和第二掺杂区之间。导电部分形成在电介质层上。

9. 发明授权

US09006068B1 MOS device with isolated drain and method for fabricating the same 有权
标题翻译：具有隔离漏极的MOS器件及其制造方法
公开(公告)号：US09006068B1
公开(公告)日：2015-04-14
申请号：US14582626
申请日：2014-12-24
申请人： MediaTek Inc
发明人： Puo-Yu Chiang , Yan-Liang Ji
IPC分类号： H01L21/266 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/266 , H01L29/0646 , H01L29/0653 , H01L29/1083 , H01L29/42368 , H01L29/7835
摘要： A method for fabricating a metal-oxide-semiconductor (MOS) device, performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate; performing a first ion implant process on two portions of the semiconductor substrate exposed by the first patterned mask layer; removing the first patterned mask layer and forming a second patterned mask layer over the semiconductor substrate, exposing a portion of the third well region; performing a second ion implant process to the portion of the third well region exposed by the second patterned mask layer; performing a third implant process to the portion of the third well region exposed by the second patterned mask layer; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.
摘要翻译：一种制造金属氧化物半导体（MOS）器件的方法，执行以下操作：形成嵌入在半导体衬底的一部分中的第一阱区; 在所述半导体衬底上形成第一图案化掩模层; 在由第一图案化掩模层曝光的半导体衬底的两个部分上执行第一离子注入工艺; 去除所述第一图案化掩模层并在所述半导体衬底上形成第二图案化掩模层，暴露所述第三阱区域的一部分; 对由第二图案化掩模层暴露的第三阱区的部分执行第二离子注入工艺; 对由第二图案化掩模层暴露的第三阱区的部分执行第三注入工艺; 在所述第三阱区域的一部分中形成源极区域; 以及在所述第五阱区的一部分中形成漏极区。

10. 发明授权

US10396166B2 Semiconductor device capable of high-voltage operation 有权
公开(公告)号：US10396166B2
公开(公告)日：2019-08-27
申请号：US15425207
申请日：2017-02-06
申请人： MEDIATEK INC.
发明人： Cheng Hua Lin , Yan-Liang Ji
IPC分类号： H01L29/40 , H01L29/10 , H01L29/66 , H01L29/78
摘要： A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.

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